參數(shù)資料
型號(hào): MAX5873EGK+TD
廠商: Maxim Integrated Products
文件頁數(shù): 2/16頁
文件大?。?/td> 0K
描述: IC DAC 12BIT DUAL 200MSPS 68-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時(shí)間: 14ns
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 300mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 68-QFN 裸露焊盤(10x10)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 4 電流,單極
采樣率(每秒): 200M
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
10
______________________________________________________________________________________
Analog Outputs
(OUTIP, OUTIN, OUTQP, OUTQN)
Each MAX5873 DAC outputs two complementary cur-
rents (OUTIP/N, OUTQP/N) that operate in a single-
ended or differential configuration. A load resistor
converts these two output currents into complementary
single-ended output voltages. A transformer or a differ-
ential amplifier configuration converts the differential
voltage existing between OUTIP (OUTQP) and OUTIN
(OUTQN) to a single-ended voltage. If not using a
transformer, the recommended termination from the
output is a 25 termination resistor to ground and a
50 resistor between the outputs.
To generate a single-ended output, select OUTIP (or
OUTQP) as the output and connect OUTIN (or OUTQN)
to GND. SFDR degrades with single-ended operation.
Figure 3 displays a simplified diagram of the internal
output structure of the MAX5873.
Clock Inputs (CLKP, CLKN)
The MAX5873 features flexible differential clock inputs
(CLKP, CLKN) operating from a separate supply
(AVCLK) to achieve the lowest possible jitter perfor-
mance. Drive the differential clock inputs from a single-
ended or a differential clock source. For single-ended
operation, drive CLKP with a logic source and bypass
CLKN to GND with a 0.1F capacitor.
CLKP and CLKN are internally biased to AVCLK / 2. This
facilitates the AC-coupling of clock sources directly to
the device without external resistors to define the DC
level. The dynamic input resistance from CLKP and
CLKN to ground is > 5k.
Data Timing Relationship
Figure 4 displays the timing relationship between digital
CMOS data, clock, and output signals. The MAX5873
features a 1.5ns hold, a -1.2ns setup, and a 1.1ns prop-
agation delay time. A nine (eight)-clock-cycle latency
exists between CLKP/CLKN, and OUTIP/OUTIN
(OUTQP/OUTQN) when operating in single-port (inter-
leaved) mode. In dual-port (parallel) mode, the clock
latency is 5.5 clock cycles for both channels.
LATCH
XOR/
DECODE
LATCH
CMOS
RECEIVER
LATCH
DAC
OUTIP
OUTIN
LATCH
XOR/
DECODE
LATCH
DAC
OUTQP
OUTQN
FSADJ
TORB
SELIQ
XOR
AVCLK
CLKN
GND
CLKP
CLK
INTERFACE
DATA11–
DATA0
1.2V
REFERENCE
POWER-DOWN
BLOCK
REFIO
DACREF
PD
GND
DVDD1.8
DVDD3.3
GND
AVDD1.8
AVDD3.3
DORI
MAX5873
Figure 1. MAX5873 High-Performance, 12-Bit, Dual Current-Steering DAC
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