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參數(shù)資料
| 型號： | MAX5858ECM+D |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 20/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT DUAL 300MSPS 48TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 設(shè)置時間： | 11ns |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 816mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP 裸露焊盤（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 300M |
MAX5858
Dual, 10-Bit, 300Msps, Current-Output DAC with
4x/2x/1x Interpolation Filters
6
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, no interpolation, external reference, VREF = 1.2V,
IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25°C guaranteed by
production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
No interpolation
34
2x interpolation
75
fDAC = 60Msps
4x interpolation
72
No interpolation
54
61
2x interpolation
146
fDAC = 165Msps
4x interpolation
140
2x interpolation
172
186
Digital Supply Current (Note 4)
IDVDD
fDAC = 200Msps
4x interpolation
165
178
mA
Clock Power-Supply Voltage
CVDD
2.7
3.3
V
fDAC = 60Msps
25
fDAC = 165Msps
69
80
Clock Supply Current (Note 4)
ICVDD
fDAC = 200Msps, 2x interpolation or 4x
interpolation
80
94
mA
Standby Current
ISTANDBY
(Note 5)
4.4
4.8
mA
Power-Down Current
IPD
(Note 5)
1
A
No interpolation
312
2x interpolation
435
fDAC = 60Msps
4x interpolation
426
No interpolation
504
570
2x interpolation
780
fDAC = 165Msps
4x interpolation
762
2x interpolation
891
Total Power Dissipation
PTOT
fDAC = 200Msps
4x interpolation
870
mW
Note 1: Including the internal reference voltage tolerance.
Note 2: Measured single ended with 50
load and complementary output connected to ground.
Note 3: Guaranteed by design, not production tested.
Note 4: fOUT = 5MHz.
Note 5: All digital inputs at 0 or DVDD. Clock signal disabled.
TO OUTPUT
PIN
5pF
0.5mA
1.6V
Figure 1. Load Test Circuit for CLK Outputs
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