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MAX5858A
Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
22
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Differential DC-Coupled Configuration
Figure 9 shows the MAX5858A output operating in differ-
ential, DC-coupled mode. This configuration can be
used in communication systems employing analog
quadrature upconverters and requiring a baseband
sampling, dual-channel, high-speed DAC for I/Q synthe-
sis. In these applications, information bandwidth can
extend from 10MHz down to several hundred kilohertz.
DC-coupling is desirable in order to eliminate long dis-
charge time constants that are problematic with large,
expensive coupling capacitors. Analog quadrature
upconverters have a DC common-mode input require-
ment of typically 0.7V to 1.0V. The MAX5858A differential
I/Q outputs can maintain the desired full-scale original
level at the required 0.7V to 1.0V DC common-mode volt-
age when powered from a single 2.85V (±5%) supply.
The MAX5858A meets this low-power requirement with
minimal reduction in dynamic range while eliminating the
need for level-shifting resistor networks.
Power Supplies, Bypassing,
Decoupling, and Layout
Grounding and power-supply decoupling strongly influ-
ence the MAX5858A performance. Unwanted digital
crosstalk can couple through the input, reference,
power-supply, and ground connections, which can
affect dynamic specifications, like signal-to-noise ratio
or spurious-free dynamic range. In addition, electro-
magnetic interference (EMI) can either couple into or
be generated by the MAX5858A. Observe the ground-
ing and power-supply decoupling guidelines for high-
speed, high-frequency applications. Follow the power
supply and filter configuration to achieve optimum
dynamic performance.
Use of a multilayer printed circuit (PC) board with sepa-
rate ground and power-supply planes is recommend-
ed. Run high-speed signals on lines directly above the
ground plane. The MAX5858A has separate analog
and digital ground buses (AGND, PGND, and DGND,
respectively). Provide separate analog, digital, and
clock ground sections on the PC board with only one
point connecting the three planes. The ground connec-
tion points should be located underneath the device
and connected to the exposed paddle. Run digital sig-
nals above the digital ground plane and analog/clock
signals above the analog/clock ground plane. Digital
signals should be kept away from sensitive analog,
clock, and reference inputs. Keep digital signal paths
short and metal trace lengths matched to avoid propa-
gation delay and data skew mismatch.
The MAX5858A includes three separate power-supply
inputs: analog (AVDD), digital (DVDD), and clock
(PVDD). Use a single linear regulator power source to
branch out to three separate power-supply lines (AVDD,
DVDD, PVDD) and returns (AGND, DGND, PGND). Filter
each power-supply line to the respective return line
using LC filters comprising ferrite beads and 10F
capacitors. Filter each supply input locally with 0.1F
ceramic capacitors to the respective return lines.
Note: To maintain the dynamic performance of the
Electrical Characteristics, ensure the voltage difference
between DVDD, AVDD, and PVDD does not exceed 150mV.
Thermal Characteristics and Packaging
Thermal Resistance
48-lead TQFP-EP:
θJA = 27.6°C/W
Keep the device junction temperature below +125°C to
meet specified electrical performance. Lower the
power-supply voltage to maintain specified perfor-
mance when the DAC update rate approaches
300Msps and the ambient temperature equals +85°C.
DA0–DA9
10
MAX5858A
1/2
50
50
PVDD
DVDD
AVDD
PGND
DGND
AGND
OUTPA
OUTNA
DB0–DB9
10
MAX5858A
50
50
OUTPB
OUTNB
Figure 9. Application with DC-Coupled Differential Outputs