參數(shù)資料
型號: MAX5841LEUB+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/15頁
文件大小: 0K
描述: IC DAC 10BIT QUAD 2WIRE 10-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
設(shè)置時間: 4µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 4 電壓,單極
采樣率(每秒): *
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
10
______________________________________________________________________________________
read operations require Sr conditions because of the
change in direction of data flow.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. ACK is always generated by the
receiving device. The MAX5841 generates an ACK
when receiving an address or data by pulling SDA low
during the ninth clock period. When transmitting data,
the MAX5841 waits for the receiving device to generate
an ACK. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communica-
tion at a later time.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by the
7-bit slave address (Figure 4). When idle, the MAX5841
waits for a START condition followed by its slave
address. The serial interface compares each address
value bit by bit, allowing the interface to power down
immediately if an incorrect address is detected. The
LSB of the address word is the Read/Write (R/W) bit.
R/W indicates whether the master is writing to or read-
ing from the MAX5841 (R/W = 0 selects the write condi-
tion, R/W = 1 selects the read condition). After
receiving the proper address, the MAX5841 issues an
ACK by pulling SDA low for one clock cycle.
The MAX5841 has four different factory/user-pro-
grammed addresses (Table 2). Address bits A6
through A1 are preset, while A0 is controlled by ADD.
Connecting ADD to GND sets A0 = 0. Connecting ADD
to VDD sets A0 = 1. This feature allows up to four
MAX5841s to share the same bus.
Write Data Format
In write mode (R/W = 0), data that follows the address
byte controls the MAX5841 (Figure 5). Bits C3–C0 con-
figure the MAX5841 (Table 3). Bits D9–D0 are DAC
data. Bits S0 and S1 are sub-bits and are always zero.
Input and DAC registers update on the falling edge of
SCL during the acknowledge bit. Should the write cycle
be prematurely aborted, data is not updated and the
write cycle must be repeated. Figure 6 shows two
example write data sequences.
Extended Command Mode
The MAX5841 features an extended command mode
that is accessed by setting C3–C0 = 1 and D9–D6 = 0.
The next data byte writes to the shutdown registers
(Figure 7). Setting bits A, B, C, or D to 1 sets that DAC
SCL
SDA
SSr
P
Figure 2. START and STOP Conditions
SCL
SDA
STOP
START
SCL
SDA
ILLEGAL
STOP
START
ILLEGAL EARLY STOP CONDITION
LEGAL STOP CONDITION
Figure 3. Early STOP Conditions
S
A6A5A4A3A2A1A0
R/W
Figure 4. Slave Address Byte Definition
C3
C2
C1
C0
D9
D8
D7
D6
Figure 5. Command Byte Definition
PART
VADD
DEVICE ADDRESS
(A6...A0)
MAX5841L
GND
0111 100
MAX5841L
VDD
0111 101
MAX5841M
GND
1011 100
MAX5841M
VDD
1011 101
Table 2. MAX5841 I2C Slave Addresses
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