參數(shù)資料
型號(hào): MAX5841LEUB+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 15/15頁(yè)
文件大?。?/td> 0K
描述: IC DAC 10BIT QUAD 2WIRE 10-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
設(shè)置時(shí)間: 4µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極
采樣率(每秒): *
產(chǎn)品目錄頁(yè)面: 1398 (CN2011-ZH PDF)
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________
9
by a START (S) or REPEATED START (Sr) condition and
a STOP (P) condition. Each word transmitted over the
bus is 8 bits long and is always followed by an
acknowledge clock pulse.
The MAX5841 SDA and SCL drivers are open-drain
outputs, requiring a pullup resistor to generate, a logic
high voltage (see Typical Operating Circuit). Series
resistors RS are optional. These series resistors protect
the input stages of the MAX5841 from high-voltage
spikes on the bus lines, and minimize crosstalk and
undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see START and
STOP Conditions). Both SDA and SCL idle high when
the I2C bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA, while SCL is high
(Figure 2). A START condition from the master signals
the beginning of a transmission to the MAX5841. The
master terminates transmission by issuing a not
acknowledge followed by a STOP condition (see
Acknowledge Bit (ACK)). The STOP condition frees the
bus. If a repeated START condition (Sr) is generated
instead of a STOP condition, the bus remains active.
When a STOP condition or incorrect address is detect-
ed, the MAX5841 internally disconnects SCL from the
serial interface until the next START condition, minimiz-
ing digital noise and feedthrough.
Early STOP Conditions
The MAX5841 recognizes a STOP condition at any
point during transmission except if a STOP condition
occurs in the same high pulse as a START condition
(Figure 3). This condition is not a legal I2C format; at
least one clock pulse must separate any START and
STOP conditions.
Repeated START Conditions
A REPEATED START (Sr) condition may indicate a
change of data direction on the bus. Such a change
read operation. Sr may also be used when the bus
master is writing to several I2C devices and does not
want to relinquish control of the bus. The MAX5841 ser-
ial interface supports continuous write operations with
or without an Sr condition separating them. Continuous
POWER-DOWN
COMMAND BITS
PD1
PD0
MODE/FUNCTION
00
Power-up device. DAC output
restored to previous value.
01
Power-down mode 0. Power down
device with output floating.
10
Power-down mode 1. Power down
device with output terminated with
1k
to GND.
11
Power-down mode 2. Power down
device with output terminated with
100k
to GND.
Table 1. Power-Down Command Bits
SCL
SDA
STOP
CONDITION
START
CONDITION
REPEATED START CONDITION
START CONDITION
tLOW
tSU, DAT
tSU, STA
tSP
tBUF
tHD, STA
tSU, STO
tR
tF
tHD, STA
tHIGH
tHD, DAT
Figure 1. 2-Wire Serial Interface Timing Diagram
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