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參數(shù)資料
| 型號(hào)： | MAX5812PEUT+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 12/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC SERIAL 12BIT 1CH SOT23-6 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 4µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 727mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | SOT-6 |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類(lèi)型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
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MAX5812
12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
8
_______________________________________________________________________________________
and a serial clock line (SCL). The MAX5812 is SMBus
compatible within the range of VDD = 2.7V to 3.6V. SDA
and SCL facilitate bidirectional communication between
the MAX5812 and the master at rates up to 400kHz.
Figure 1 shows the 2-wire interface timing diagram. The
MAX5812 is a transmit/receive slave-only device, rely-
ing upon a master to generate a clock signal. The mas-
ter, typically a microcontroller, initiates data transfer on
the bus and generates SCL to permit that transfer.
A master device communicates to the MAX5812 by
transmitting the proper address followed by command
and/or data words. Each transmit sequence is framed
by a START (S) or REPEATED START (Sr) condition and
a STOP (P) condition. Each word transmitted over the
bus is 8 bits long and is always followed by an
acknowledge clock pulse.
The MAX5812 SDA and SCL drivers are open-drain out-
puts, requiring a pullup resistor (500
or greater) to
generate a logic high voltage (see the Typical Operating
Circuit). Series resistors RS are optional. These series
resistors protect the input stages of the MAX5812 from
high-voltage spikes on the bus lines and minimize
crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while the SCL is high are control signals (see the
START and STOP Conditions section). SDA and SCL
idle high when the I2C bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
Figure 1. Two-Wire Serial lnterface Timing Diagram
SCL
SDA
STOP
CONDITION
START
CONDITION
REPEATED START CONDITION
START CONDITION
tLOW
tSU, DAT
tSU, STA
tSP
tBUF
tHD, STA
tSU, STO
tR
tF
tHD, STA
tHIGH
tHD, DAT
SCL
SDA
SSr
P
Figure 2. START/STOP Conditions
Figure 3. Early STOP condition
SCL
SDA
STOP
START
SCL
SDA
ILLEGAL
STOP
START
ILLEGAL EARLY STOP CONDITION
LEGAL STOP CONDITION
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