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參數(shù)資料
| 型號： | MAX5774UTK+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 28/28頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 32CH V-OUT 68-TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 設置時間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 32 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-TQFN 裸露焊盤 |
| 供應商設備封裝： | 68-TQFN-EP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 32 電壓，單極 |
| 采樣率（每秒）： | * |
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MAX5773/MAX5774/MAX5775
32-Channel, 14-Bit, Voltage-Output
DACs with Serial Interface
_______________________________________________________________________________________
9
TIMING CHARACTERISTICS (continued)
(Figures 1 and 2, AVDD = +4.75V to +5.25V, DVDD = +4.75V to +5.25V, AGND = DGND = REFGND = GS1 = GS2 = 0, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CS Fall to SCLK Fall Setup Time
tCSS
5ns
CS Rise to SCLK Fall
tCS1
At end of cycle in SPI mode only
15
ns
SCLK Fall to
CS Rise Setup Time
tCS2
0ns
DIN to SCLK Fall Setup Time
tDS
10
ns
DIN to SCLK Fall Hold Time
tDH
2ns
SCLK Fall to DOUT Fall
tSCL
Load capacitance = 20pF
20
ns
SCLK Fall to DOUT Rise
tSDH
Load capacitance = 20pF
20
ns
CS Pulse-Width High
tCSPWH
50
ns
CS Pulse-Width Low
tCSPWL
(Note 7)
20
ns
LDAC Pulse-Width Low
tLDAC
20
ns
RESET Pulse-Width Low
tCLR
50
ns
TIMING CHARACTERISTICS
(Figures 1 and 2, AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.25V, AGND = DGND = REFGND = GS1 = GS2 = 0, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency
fSCLK
0
25
MHz
SCLK Pulse-Width High
tCH
10
ns
SCLK Pulse-Width Low
tCL
10
ns
SCLK Fall to
CS Fall Setup Time
tSCS
10
ns
CS Fall to SCLK Fall Setup Time
tCSS
10
ns
CS Rise to SCLK Fall
tCS1
At end of cycle in SPI mode only
18
ns
SCLK Fall to
CS Rise Setup Time
tCS2
0ns
DIN to SCLK Fall Setup Time
tDS
10
ns
DIN to SCLK Fall Hold Time
tDH
2ns
SCLK Fall to DOUT Fall
tSCL
Load capacitance = 20pF
25
ns
SCLK Fall to DOUT Rise
tSDH
Load capacitance = 20pF
25
ns
CS Pulse-Width High
tCSPWH
50
ns
CS Pulse-Width Low
tCSPWL
(Note 7)
20
ns
LDAC Pulse-Width Low
tLDAC
20
ns
RESET Pulse-Width Low
tCLR
50
ns
Note 1: AVCC should be at least 0.25V higher than the maximum output voltage required from the DAC.
Note 2: Linearity guaranteed for full code range.
Note 3: Offset error is measured at code 0. Gain error is measured at code 3FFFh.
Note 4: DC crosstalk is the change in the output level of one DAC at midscale in response to the full-scale output change of all other DACs.
Note 5: Digital feedthrough is a measure of the impulse injected into the analog outputs from the digital control inputs when the
device is not being written to. It is measured with a worst-case change on the digital inputs.
Note 6: DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one converter due to both the digital change and
subsequent analog output change at another converter.
Note 7: In DSP mode, maintain the maximum CS pulse width low to
≤ 16 SCLK cycles.
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