參數(shù)資料
型號: MAX5774UCB+TD
廠商: Maxim Integrated Products
文件頁數(shù): 6/28頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 32CHAN SER 64-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 750
設(shè)置時間: 20µs
位數(shù): 14
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 32
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 32 電壓,單極
采樣率(每秒): *
MAX5773/MAX5774/MAX5775
Detailed Description
The MAX5773/MAX5774/MAX5775 are 32-channel, 14-
bit, voltage-output DACs. All devices accept a +3.0V
external reference input at REF. An internal offset DAC
allows all outputs to be offset up to -5V (see Table 1).
A 33MHz SPI-/QSPI-/MICROWIRE- or DSP-compatible
serial interface (see Figure 1) controls the
MAX5773/MAX5774/MAX5775. Use DSP to select the
DSP mode or the SPI/QSPI/MICROWIRE mode.
Each DAC has a double-buffered input structure to
minimize the digital-noise feedthrough from the digital
inputs to the outputs. The two buffers are organized as
an input register followed by a DAC register. Input reg-
isters update the DAC registers independently or simul-
taneously with a single software or hardware command.
Each DAC channel has its own offset and gain registers
that calibrate offset and gain errors for a given channel.
The MAX5773/MAX5774/MAX5775 are divided into two
banks of 16 channels to provide real-time calibration of
channel pairs. Channel bank pairs are ordered as
(bank 0:bank 1) OUT0:OUT16, OUT1:OUT17 …
OUT14:OUT30, OUT15:OUT31.
An offset DAC allows all the outputs to be offset up to
-5V and dual ground-sensing inputs (GS1 and GS2)
allow the output voltages to be referenced to remote
32-Channel, 14-Bit, Voltage-Output
DACs with Serial Interface
14
______________________________________________________________________________________
Pin Description
PIN
68 TQFN
64 TQFP
NAME
FUNCTION
31
30
REF
Analog Reference Voltage Input. Connect a +3V reference to REF and bypass to
REFGND with a 0.1F capacitor.
32, 61
31, 57
AVDD
Analog Power-Supply Input. Bypass to AGND with a 0.1F capacitor.
37
35
OUT16
DAC16 Buffered Analog Output Voltage
38
36
OUT17
DAC17 Buffered Analog Output Voltage
39
37
OUT18
DAC18 Buffered Analog Output Voltage
40
38
OUT19
DAC19 Buffered Analog Output Voltage
41
39
OUT20
DAC20 Buffered Analog Output Voltage
42
40
OUT21
DAC21 Buffered Analog Output Voltage
43
41
OUT22
DAC22 Buffered Analog Output Voltage
44
42
OUT23
DAC23 Buffered Analog Output Voltage
45
43
OUT24
DAC24 Buffered Analog Output Voltage
48
46
OUT25
DAC25 Buffered Analog Output Voltage
49
47
OUT26
DAC26 Buffered Analog Output Voltage
54
50
OUT27
DAC27 Buffered Analog Output Voltage
55
51
OUT28
DAC28 Buffered Analog Output Voltage
56
52
OUT29
DAC29 Buffered Analog Output Voltage
57
53
OUT30
DAC30 Buffered Analog Output Voltage
58
54
OUT31
DAC31 Buffered Analog Output Voltage
62
58
OUT15
DAC15 Buffered Analog Output Voltage
63
59
OUT14
DAC14 Buffered Analog Output Voltage
64
60
OUT13
DAC13 Buffered Analog Output Voltage
65
61
OUT12
DAC12 Buffered Analog Output Voltage
66
62
OUT11
DAC11 Buffered Analog Output Voltage
67
63
OUT10
DAC10 Buffered Analog Output Voltage
EP
EP
Exposed Paddle. Connect to VSS.
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