參數(shù)資料
型號: MAX5632UCB+D
廠商: Maxim Integrated Products
文件頁數(shù): 10/15頁
文件大?。?/td> 0K
描述: IC DAC 16BIT 32CH S&H 64-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
位數(shù): 16
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 32
電壓電源: 雙 ±
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
輸出數(shù)目和類型: 32 電壓,單極
采樣率(每秒): *
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
4
Maxim Integrated
Note 1: The nominal zero-scale (code = 0) voltage is -4.0535V. The nominal full-scale (code = FFFF hex) voltage is +9.0535V. The
output voltage is limited by the Output Range specification, restricting the useable range of DAC codes. The nominal zero-
scale voltage may be achieved when VSS < -4.9V, and the nominal full-scale voltage may be achieved when VDD > +11.5V.
Note 2: Gain is calculated from measurements
for voltages VDD = 10V and VSS = -4V at codes C000 hex and 4F2C hex,
for voltages VDD = 11.6V and VSS = -2.9V at codes FFFF hex and 252E hex,
for voltages VDD = 9.25V and VSS = -5.25V at codes D4F6 hex and 0 hex, and
for voltages VDD = 8.55V and VSS = -2.75V at codes C74A hex and 281C hex.
Note 3: Steady-state change in any output with an 8V change in an adjacent output.
Note 4: Settling during the first update for an 8V step. The output will settle to within the linearity specification on subsequent
updates. Tested with an external sequencer clock frequency of 480kHz.
Note 5: External clock mode with the external clock not toggling.
Note 6: The output voltage is the sum of the DAC output and the voltage at GS. GS gain is measured at 4F2C hex.
Note 7: The sequencer runs at fSEQ = fECLK/4. Maximum speed is limited by settling of the DAC and SHAs. Minimum speed is
limited by acceptable droop and update time after a Burst Mode Update.
Note 8: VDD rise to CS low = 500s maximum.
Note 9: Guaranteed by gain-error test.
Note 10: The serial interface is inactive. VIH = VLOGIC, VIL = 0V.
Note 11: The serial interface is active. VIH = VLOGIC, VIL = 0V.
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, VAGND = VDGND = VGS = 0V, RL ≥ 10M, CL = 50pF,
CLKSEL = +5V, fECLK = 400kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK High to
CS High Hold Time
tCSH1
0ns
DIN to SCLK High Setup Time
tDS
15
ns
DIN to SCLK High Hold Time
tDH
0ns
RST to CS Low
(Note 8)
500
s
POWER SUPPLIES
Positive Supply Voltage
VDD
(Note 9)
8.55
10
11.6
V
Negative Supply Voltage
VSS
(Note 9)
-5.25
-4
-2.75
V
Supply Difference
VDD - VSS (Note 9)
14.5
V
Logic Supply Voltage
VLOGIC,
VLDAC,
VLSHA
4.75
5
5.25
V
Positive Supply Current
IDD
32
42
mA
Negative Supply Current
ISS
32
40
mA
(Note 10)
1
1.5
Logic Supply Current
ILOGIC
fSCLK = 20MHz (Note 11)
2
3
mA
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