參數(shù)資料
型號: MAX5580BEUP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
中文描述: SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO20
封裝: 4.40 MM, MO-153ACT, TSSOP-20
文件頁數(shù): 5/36頁
文件大?。?/td> 1018K
代理商: MAX5580BEUP
M
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= 2.7V to 5.25V, DV
DD
= 1.8V to AV
DD
, AGND = 0, DGND = 0, V
REF
= 2.5V (for AV
DD
= 2.7V to 5.25V), V
REF
= 4.096V (for
AV
DD
= 4.5V to 5.25V), R
L
= 10k
, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25
°
C.) (Note 1)
PARAMETER
POWER REQUIREMENTS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Analog Supply Voltage
Range
AV
DD
2.70
5.25
V
Digital Supply Voltage
Range
DV
DD
1.8
AV
DD
V
Unity gain
0.9
1.6
SLOW mode, all digital inputs
at DGND or DV
DD
, no load,
V
REF
= 4.096V
FAST mode, all digital inputs
at DGND or DV
DD
, no load,
V
REF
= 4.096V
Force sense
1.6
2.4
Unity gain
1.6
4
Operating Supply
Current
I
AVDD
+
I
DVDD
Force sense
2.3
4
mA
Shutdown Supply
Current
I
AV D D S H D N
+
I
D V D D S H D N
No clocks, all digital inputs at DGND or DV
DD
, all
DACs in shutdown mode
0.5
1
μA
Note 1:
For the force-sense versions, FB_ is connected to its respective OUT_, and VOUT (max) = VREF / 2, unless otherwise noted.
Note 2:
Linearity guaranteed from decimal code 250 to code 4095 for the MAX5580A/MAX5581A (12 bit, A grade), code 40 to code
4095 for the MAX5580B/MAX5581B (12 bit, B grade), code 20 to code 1023 for the MAX5582/MAX5583 (10 bit), and code 5
to code 255 for the MAX5584/MAX5585 (8 bit).
Note 3:
Represents the functional range. The linearity is guaranteed at VREF= 2.5V (for AVDDfrom 2.7V to 5.25V), and VREF=
4.096V (for AVDD= 4.5V to 5.25V). See the
Typical Operating Characteristics
section for linearity at other voltages.
Note 4:
Guaranteed by design.
Note 5:
The reference -3dB bandwidth is measured with a 0.1VP-Psine wave on VREFand with full-scale input code.
Note 6:
DC crosstalk is measured as follows: outputs of DACA–DACD are set to full scale and the output of DACD is measured.
While keeping DACD unchanged, the outputs of DACA–DACC are transitioned to zero scale and the
VOUTof DACD
is measured.
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