Self-Biased Two-Electrode
Potentiostat Application
See the circuit in Figure 10 for an illustration of how to
use the MAX5515 to bias a two-electrode potentiostat
on the input of an ADC.
Power Supply and
Bypassing Considerations
Bypass the power supply with a 0.1F capacitor to GND.
Minimize lengths to reduce lead inductance. If noise
becomes an issue, use shielding and/or ferrite beads to
increase isolation. For the thin QFN package, connect the
exposed pad to ground.
Layout Considerations
Digital and AC transient signals coupling to GND can
create noise at the output. Use proper grounding tech-
niques, such as a multilayer board with a low-inductance
ground plane. Wire-wrapped boards and sockets are not
recommended. For optimum system performance, use
printed circuit (PC) boards. Good PC board ground lay-
out minimizes crosstalk between DAC outputs, reference
inputs, and digital inputs. Reduce crosstalk by keeping
analog lines away from digital lines.
MAX5512–MAX5515
Dual, Ultra-Low-Power,
8-Bit, Voltage-Output DACs
______________________________________________________________________________________
19
H
L
FB
W
NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
NPOT IS THE NUMERIC VALUE OF THE POT INPUT CODE.
REFIN
1/2 MAX5514
MAX5401
SOT-POT
100k
DAC
VOUT
5PPM/°C
RATIOMETRIC
TEMPCO
1.8V ≤ VDD ≤ 5.5V
VOUT
VOUT =
VREFIN × NDAC
256
(1 +
255 - NPOT)
255
SCLK
DIN
CS2
CS1
Figure 9. Software-Configurable Output Gain
DAC
BAND
GAP
TO ADC
OUT
REFOUT
REF
1/2 MAX5515
TO ADC
FB
WE
SENSOR
CE
IF
RF
CL
Figure 10. Self-Biased Two-Electrode Potentiostat Application
NDACA IS THE NUMERIC VALUE
OF THE DAC A INPUT CODE.
REFIN
DAC
VOUT1
VOUT1 =
VREFIN × NDACA
256
(1 +
R2 )
R1
NDACB IS THE NUMERIC VALUE
OF THE DAC B INPUT CODE.
VOUT2 =
VREFIN × NDACB
256
VOUTA
1/2 MAX5514
FBA
DAC
VOUT2
VOUTB
FBB
R2
R1
Figure 8. Separate Force-Sense Outputs Create Unity and
Greater-than-Unity DAC Gains Using the Same Reference