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參數(shù)資料
型號(hào): MAX5481EUD+T
廠商: Maxim Integrated Products
文件頁數(shù): 15/20頁
文件大小: 0K
描述: IC POT DGTL 10BIT NV 14-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
接片: 1024
電阻(歐姆): 10k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 35 ppm/°C
存儲(chǔ)器類型: 非易失
接口: 4 線串行(芯片選擇,遞增,增/減)
電源電壓: 2.7 V ~ 5.25 V,±2.5 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 帶卷 (TR)
10-Bit, Nonvolatile, Linear-Taper Digital
Potentiometers
TIMING CHARACTERISTICS
(VDD = +2.7V to +5.25V, VSS = VGND = 0V, VH = VDD, VL = 0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
VDD = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG SECTION
MAX5481
5
Wiper Settling Time (Note 6)
tS
MAX5482
22
s
SPI-COMPATIBLE SERIAL INTERFACE (Figure 3)
SCLK Frequency
fSCLK
7
MHz
SCLK Clock Period
tCP
140
ns
SCLK Pulse-Width High
tCH
60
ns
SCLK Pulse-Width Low
tCL
60
ns
CS Fall to SCLK Rise Setup
tCSS
60
ns
SCLK Rise to CS Rise Hold
tCSH
0ns
DIN to SCLK Setup
tDS
40
ns
DIN Hold after SCLK
tDH
0ns
SCLK Rise to CS Fall Delay
tCS0
15
ns
CS Rise to SCLK Rise Hold
tCS1
60
ns
CS Pulse-Width High
tCSW
150
ns
Write NV Register Busy Time
tBUSY
12
ms
UP/DOWN DIGITAL INTERFACE (Figure 8)
CS to INC Setup
tCI
25
ns
INC High to U/D Change
tID
20
ns
U/D to INC Setup
tDI
25
ns
INC Low Period
tIL
25
ns
INC High Period
tIH
25
ns
INC Inactive to CS Inactive
tIC
50
ns
CS Deselect Time (Store)
tCPH
50
ns
INC Cycle Time
tCYC
50
ns
INC Active to CS Inactive
tIK
50
ns
Wiper Store Cycle
tWSC
12
ms
Note 1: 100% production tested at TA = +25°C and TA = +85°C. Guaranteed by design to TA = -40°C.
Note 2: The DNL and INL are measured with the device configured as a voltage-divider with H = VDD and L = VSS. The wiper termi-
nal (W) is unloaded and measured with a high-input-impedance voltmeter.
Note 3: The DNL_R and INL_R are measured with D.N.C. unconnected and L = VSS = 0V. For VDD = +5V, the wiper terminal is dri-
ven with a source current of IW = 80A for the 50kΩ device and 400A for the 10kΩ device. For VDD = +3V, the wiper termi-
nal is driven with a source current of 40A for the 50kΩ device and 200A for the 10kΩ device.
Note 4: The wiper resistance is measured using the source currents given in Note 3.
Note 5: The device draws higher supply current when the digital inputs are driven with voltages between (VDD - 0.5V) and (VGND +
0.5V). See Supply Current vs. Digital Input Voltage in the
Typical Operating Characteristics.
Note 6: Wiper settling test condition uses the voltage-divider configuration with a 10pF load on W. Transition code from 00000 00000
to 01111 01111 and measure the time from
CS going high to the wiper voltage settling to within 0.5% of its final value.
MAX5481–MAX5484
4
Maxim Integrated
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