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參數(shù)資料
| 型號(hào)： | MAX5435MEZT+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 19/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL 32TAP NV TSOT23-6 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接片： | 32 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 35 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 細(xì)型，TSOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | TSOT-23-6 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1399 (CN2011-ZH PDF) |
| 其它名稱： | MAX5435MEZT+TDKR |
MAX5432–MAX5435
32-Tap, Nonvolatile, I2C, Linear, Digital
Potentiometers
_______________________________________________________________________________________
9
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 5).
Acknowledge
The acknowledge bit is a clocked 9th bit that the recip-
ient uses to handshake receipt of each byte of data
(Figure 6). Each byte transferred effectively requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge
clock pulse, so the SDA line is stable low during the
high period of the clock pulse. When the master trans-
mits to the MAX5432–MAX5435, the devices generate
the acknowledge bit because the MAX5432–MAX5435
are the recipients.
Slave Address
The MAX5432–MAX5435 have a 7-bit-long slave
address (Figure 4). The 8th bit following the 7-bit slave
address is the NOP/W bit. Set the NOP/W bit low for a
write command and high for a no-operation command.
Table 1a shows four possible slave addresses for the
MAX5432/MAX5433 and Table 1b shows three possible
slave addresses for the MAX5434/MAX5435. The first 4
bits (MSBs) of the slave addresses are always 0101.
Bits A2 and A1 are factory programmed for the
MAX5432/MAX5433 (Table 1a). Connect the A0 input
(MAX5432/MAX5433 only) to either GND or VDD to
select one of two I2C device addresses. Each device
must have a unique address to share the bus. A maxi-
mum of four MAX5432/MAX5433 devices can share the
same bus. Bits A2, A1, and A0 are factory programmed
for the MAX5434/MAX5435 (Table 1b).
Message Format for Writing
A write to the MAX5432–MAX5435 consists of the trans-
mission of the device’s slave address with the 8th bit set
to zero, followed by at least 1 byte of information. The
1st byte of information is the command byte. The bytes
received after the command byte are the data bytes.
The 1st data byte goes into the internal register of the
MAX5432–MAX5435 as selected by the command byte
(Figure 8).
tHD-STA
tSU-DAT
tHIGH
tR
tF
tHD-DAT
tHD-STA
S
Sr
A
tSU-STA
tLOW
tBUF
tSU-STO
PS
tR
tF
SCL
SDA
PARAMETERS ARE MEASURED FROM 30% TO 70%.
Figure 1. I2C Serial-Interface Timing Diagram
ADDRESS BYTE
PART
SUFFIX
A6
A5
A4
A3
A2
A1
A0
NOP/
W
L
0
1
01
000
NOP/W
M
0
1
01
100
NOP/W
N*
0
1
01
010
NOP/W
ADDRESS BYTE
PART
SUFFIX
A6
A5
A4
A3
A2
A1
A0
NOP/
W
L
0101000
NOP/W
L
0101001
NOP/W
M
0101100
NOP/W
M
0101101
NOP/W
Table 1a. Address Codes
(MAX5432/MAX5433 Only)
Table 1b. Address Codes
(MAX5434/MAX5435 Only)
*MAX5434 only.
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