參數(shù)資料
型號: MAX5393LAUD+T
廠商: Maxim Integrated Products
文件頁數(shù): 14/14頁
文件大小: 0K
描述: IC POT DGTL DUAL 256TAP 14TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
接片: 256
電阻(歐姆): 10k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 35 ppm/°C
存儲器類型: 易失
接口: 3 線串行(芯片選擇)
電源電壓: 1.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 帶卷 (TR)
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
MAX5391/MAX5393
_______________________________________________________________________________________ 9
Detailed Description
The MAX5391/MAX5393 dual 256-tap, volatile, low-volt-
age linear taper digital potentiometers offer three end-to-
end resistance values of 10kI, 50kI, and 100kI. Each
potentiometer consists of 255 fixed resistors in series
between terminals H_ and L_. The potentiometer wiper,
W_, is programmable to access any one of the 256 tap
points on the resistor string.
The potentiometers in each device are programmable
independently of each other. The MAX5391/MAX5393
feature an SPI interface.
Charge Pump
The MAX5391/MAX5393 contain an internal charge
pump that guarantees the maximum wiper resistance,
RWL, to be less then 200I for supply voltages down to
1.7V. Pins H_, W_, and L_ are still required to be less
than VDD + 0.3V. A bypass input, BYP, is provided to
allow additional filtering of the charge-pump output, fur-
ther reducing clock feed through that may occur on H_,
W_, or L_. The nominal clock rate of the charge pump
is 600kHz. BYP should remain resistively unloaded as
any additional load would produce a ripple of approxi-
mately IBYP/(600kHz x CBYP) volts. See the Charge-
Pump Feedthrough at W_ vs. CBYP graph in the Typical
Operating Characteristics for CBYP sizing guidelines with
respect to clock feedthrough to the wiper. The value of
CBYP does affect the startup time of the charge pump;
however, CBYP does not impact the ability to commu-
nicate with the device, nor is there a minimum CBYP
requirement. The maximum wiper impedance specifi-
cation is not guaranteed until the charge pump is fully
settled. See the BYP Ramp vs. CBYP graph in the Typical
Operating Characteristics for CBYP impact on charge-
pump settling time.
SPI Digital Interface
The MAX5391/MAX5393 include a SPI interface that pro-
vides a 3-wire write-only serial-data interface to control
the wiper tap position through inputs chip select (CS),
data in (DIN), and data clock (SCLK). Drive CS low to
load data from DIN synchronously into the serial shift
register on the rising edge of each SCLK pulse. The
MAX5391/MAX5393 load the last 10 bits of clocked data
into the appropriate potentiometer control register once
CS transitions high. See Figures 2 and 3. Data written
to a memory register immediately updates the wiper
position. Keep CS low during the entire data stream to
prevent the data from being terminated.
The first two bits A1:A0 (address bits) address one of
the two potentiometers. See Table 1. The power-on reset
(POR) circuitry sets the wiper to midscale.
Table 1. SPI Register Map
Figure 2. SPI Digital Interface Format
Bit Number
1
2
3
4
5
6
7
8
9
10
Bit Name
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write Wiper Register A
0
D7
D6
D5
D4
D3
D2
D1
D0
Write Wiper Register B
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Write to Both A and B
1
D7
D6
D5
D4
D3
D2
D1
D0
CS
COMMAND
STARTED 10-BIT
SCLK
DIN
A0
A1
D7
D6
D5
D4
D3
D2
D0
D1
WIPER REGISTER
LOADED
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