參數(shù)資料
型號: MAX5383EZT+T
廠商: Maxim Integrated Products
文件頁數(shù): 10/15頁
文件大?。?/td> 0K
描述: IC DAC 8BIT 3WIRE SER TSOT23-6
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時間: 20µs
位數(shù): 8
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-6 細型,TSOT-23-6
供應(yīng)商設(shè)備封裝: TSOT-23-6
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極
采樣率(每秒): *
MAX5383/MAX5384/MAX5385
Low-Cost, Low-Power, 8-Bit DACs with 3-Wire
Serial Interface in SOT23
4
_______________________________________________________________________________________
-0.050
-0.075
-0.100
0
-0.025
0.025
0.050
0.075
INTEGRAL NONLINEARITY vs. CODE
MAX5383/4/5-01
CODE
INL
(LSB)
0
100
150
50
200
250
300
0
-0.10
-0.20
2.5
4.0
3.0
3.5
4.5
5.0
5.5
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX5383/4/5-02
SUPPLY VOLTAGE (V)
INL
(LSB)
-0.05
-0.15
0
-0.025
-0.050
-40
20
-20
0
40
60
80
100
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX5383/4/5-03
TEMPERATURE (°C)
INL
(LSB)
-0.020
-0.010
-0.015
-0.005
0
0.005
0.010
0
100
200
300
DIFFERENTIAL NONLINEARITY vs. CODE
MAX5383/4/5-04
CODE
DNL
(LSB)
0
-0.015
-0.020
-0.010
-0.005
-0.025
2.5
4.0
3.0
3.5
4.5
5.0
5.5
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX5383/4/5-05
SUPPLY VOLTAGE (V)
DNL
(LSB)
0
-0.010
-0.015
-0.020
-0.005
-0.025
-40
20
-20
0
40
60
80
100
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
MAX5383/4/5-06
TEMPERATURE (°C)
DNL
(LSB)
Typical Operating Characteristics
(VDD = +3.0V (MAX5383), VDD = +5.0V (MAX5384/MAX5385), TA = +25°C, unless otherwise noted.)
TIMING CHARACTERISTICS (continued)
(Figures 3 and 4, VDD = +2.7V to +3.6V (MAX5383), VDD = +4.5V to +5.5V (MAX5384), VDD = +2.7V to +5.5V (MAX5385),
RL = 10k, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) (Note 7)
Note 1: Guaranteed from code 5 to code 255.
Note 2: The offset value extrapolated from the range over which the INL is guaranteed.
Note 3: MAX5385 tested at 5V ±10%.
Note 4: MAX5383 tested at 3V ±10%; MAX5384 tested at 5V ±10%.
Note 5: Actual output voltages at full-scale are 255/256 VREF.
Note 6: Output settling time is measured by stepping from code 5 to code 255, and from code 255 to code 5.
Note 7: Guaranteed by design.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CS Rise to SCLK Rise Hold
tCS1
40
ns
CS Pulse Width High
tCSW
100
ns
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