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參數資料
| 型號： | MAX5382PEUK+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 2/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT 2WIRE SER SOT23-5 |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 設置時間： | 20µs |
| 位數： | 8 |
| 數據接口： | 串行 |
| 轉換器數目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 571mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74A，SOT-753 |
| 供應商設備封裝： | SOT-23-5 |
| 包裝： | 帶卷 (TR) |
| 輸出數目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
MAX5380/MAX5381/MAX5382
device, followed by the MAX5380/MAX5381/MAX5382s’
preset slave address, a power-mode bit, the DAC data,
and finally, a STOP condition (Figure 6). The bus is then
free for another transmission.
SDA’s state is sampled and therefore must remain sta-
ble while SCL is high. Data is transmitted in 8-bit bytes.
Nine clock cycles are required to transfer each byte to
the MAX5380/MAX5381/MAX5382. Release SDA during
the 9th clock cycle since the selected device acknowl-
edges receipt of the byte by pulling SDA low during
this time. A series resistor on the SDA line may be
needed if the master’s output is forced high while the
selected device acknowledges (Figure 4).
Slave Address
The MAX5380/MAX5381/MAX5382 are available with
one of four preset slave addresses. Each address
option is identified by the suffix L, M, N, or P added to
the part number. The address is defined as the 7MSBs
sent by the master after a START condition. The
address options are 0x60, 0x62, 0x64, 0x66 (left justi-
fied with LSB set to 0). The 8th bit, typically used to
define a write or read protocol, sets the device’s power
mode (SHDN). The device is powered-down when
SHDN is set to one. During a device search routine, the
MAX5380/MAX5381/MAX5382 acknowledge both
options (SHDN = 0 or SHDN = 1), but do not change
their power state if a stop condition (or restart) is issued
immediately. The second byte (DAC data) must be
sent/received for the device to update both power
mode and DAC output.
DAC Data
The 8-bit DAC data is decoded as straight binary MSB
first with 1LSB = VREF / 256 and converted into the cor-
responding analog voltage as shown in Table 1. After
receiving the data byte, the devices acknowledge its
receipt and expect a STOP condition, at which point
the DAC output is updated.
The MAX5380/MAX5381/MAX5382 update the output
and the power mode only if the second byte is clocked
in (SHDN = 0) or out (SHDN = 1) of the device. When
SHDN = 1, the master will read all ones when clocking
out a data byte. The MAX5380/MAX5381/MAX5382 do
not drive SDA except for the acknowledge bit.
I2C Compatibility
The MAX5380/MAX5381/MAX5382 are compatible with
existing I2C systems. SCL and SDA are high-imped-
ance inputs; SDA has an open drain that pulls the data
line low during the 9th clock pulse. Figure 7 shows a
typical I2C application. The communication protocol
supports standard I2C 8-bit communications. The gen-
eral call address is ignored, and CBUS formats are not
supported. The devices’ address is compatible with the
7-bit I2C addressing protocol only. No 10-bit formats
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
10
______________________________________________________________________________________
*SEE ORDERING INFORMATION.
SDA
START
CONDITION
STOP
CONDITION
9
8
10
18
1
17
ACK
LSB
MSB
LSB
MSB
0
1
0
A1
0
A2
ACK
SHDN
D7
D5
D6
D4
D2
D3
D1
D0
SLAVE ADDRESS BYTE
DAC CODE
*
A1 A2
0
L
0
1
M
1
0
N
11
P
Figure 6. A Complete Serial Transmission
SCL
SDA
START CONDITION
STOP CONDITION
Figure 5. START and STOP Conditions
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