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參數(shù)資料
型號: MAX537BCPE
廠商: Maxim Integrated Products
文件頁數(shù): 8/24頁
文件大?。?/td> 0K
描述: IC DAC QUAD CALBRTD 12BIT 16-DIP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 25
設(shè)置時間: 3µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 雙 ±
功率耗散(最大): 842mW
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 16-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 16-PDIP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): *
MAX536/MAX537
When daisy-chaining MAX536s, the delay from CS
low to SCK high (tCSS) must be the greater of:
tDV + tDS
or
tTR + tRC + tDS - tCSW
where tRC is the time constant of the external pullup resistor
(Rp) and the load capacitance (C) at SDO. For tRC < 20ns,
tCSS is simply tDV + tDS. Calculate tRC from the following
equation:
tRC = Rp (C)
ln
where VPULLUP is the voltage to which the pullup resistor is
connected.
Additionally, when daisy-chaining devices, the maximum
clock frequency is limited to:
1
fSCK(max) = ——————————————
2 (tDO + tRC - 38ns + tDS)
For example, with tRC = 23ns (5V ±10% supply with
Rp = 1k
and C = 30pF), the maximum clock frequency is
8.7MHz.
Figure 9 shows an alternate method of connecting several
MAX536/MAX537s. In this configuration, the data bus is
common to all devices; data is not shifted through a
daisy-chain. More I/O lines are required in this configu-
ration because a dedicated chip-select input (CS) is
required for each IC.
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
16
______________________________________________________________________________________
VPULLUP
VPULLUP - 2.4V
Table 1. Serial-Interface Programming Commands
“X” = Don’t Care. LDAC provides true latch control: when LDAC is low, the DAC registers are transparent; when LDAC is high,
the DAC registers are latched.
Mode 0, DOUT clocked out on SCK’s falling edge. All DACs
updated from their respective input registers.
Mode 1 (default condition at power-up), DOUT clocked out on
SCK’s rising edge. All DACs updated from their respective
input registers.
Load DAC D input register; DAC D is immediately updated.
0
12-bit DAC data
1
X
1
Load DAC C input register; DAC C is immediately updated.
0
12-bit DAC data
1
X
0
1
Load DAC B input register; DAC B is immediately updated.
0
12-bit DAC data
1
X
1
0
Load DAC A input register; DAC A is immediately updated.
0
12-bit DAC data
1
0
X
0
X
XXXXXXXXXXXX
0
1
0
1
X
XXXXXXXXXXXX
0
1
Update all DACs from their respective input registers.
1
XXXXXXXXXXXX
0
1
X
0
No operation (NOP)
X
XXXXXXXXXXXX
0
1
X
Load all DACs from shift register.
X
12-bit DAC data
0
X
Load input register D; all DAC registers updated.
1
12-bit DAC data
1
Load input register C; all DAC registers updated.
1
12-bit DAC data
1
0
1
Load input register B; all DAC registers updated.
1
12-bit DAC data
1
0
Load input register A; all DAC registers updated.
1
12-bit DAC data
1
0
Load DAC D input register; DAC output unchanged.
1
12-bit DAC data
1
0
1
Load DAC C input register; DAC output unchanged.
1
12-bit DAC data
1
0
1
Load DAC B input register; DAC output unchanged.
1
12-bit DAC data
1
0
1
0
Load DAC A input register; DAC output unchanged.
1
12-bit DAC data
1
0
D11…D0
C0
C1
A0
A1
FUNCTION
LDAC
16-BIT SERIAL WORD
()
[
]
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