參數(shù)資料
型號(hào)： MAX537AEWE+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 19/24頁(yè)
文件大小： 0K
描述： IC DAC 12BIT QUAD CALIB 16-SOIC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1,000
設(shè)置時(shí)間： 3µs
位數(shù)： 12
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 雙 ±
功率耗散（最大）： 762mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC W
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 4 電壓，單極；4 電壓，雙極
采樣率（每秒）： *
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX536 (continued)
(VDD = +12V, VSS = -5V, REFAB/REFCD = 8V, AGND = DGND = 0V, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
tPOR
20
s
SCK Clock Period
tCP
100
ns
SCK Pulse Width High
tCH
30
ns
SCK Pulse Width Low
tCL
30
ns
tCSS
20
ns
tCSH
10
ns
SDI Setup Time
tDS
40
26
ns
SDI Hold Time
tDH
0
ns
tDO1
1k
pullup on SDO
to VDD, CLOAD = 50pF
SDO high
78
105
ns
SDO low
50
80
SCK Fall to SDO Valid
Propagation Delay (Note 7)
tDO2
1k
pullup on SDO
to VDD, CLOAD = 50pF
SDO high
81
110
ns
SDO low
53
85
tDV
27
45
ns
tTR
40
60
ns
SCK Rise to CS Fall Delay
tCS0
Continuous SCK, SCK edge ignored
20
ns
tCS1
SCK edge ignored
20
ns
LDAC Pulse Width Low
tLDAC
30
ns
CS Pulse Width High
tCSW
40
ns
Internal Power-On Reset
Pulse Width (Note 2)
CS Fall to SCK Rise
Setup Time
SCK Rise to CS Rise
Hold Time
SCK Rise to SDO Valid
Propagation Delay (Note 6)
CS Fall to SDO Enable
(Note 8)
CS Rise to SDO Disable
(Note 9)
CS Rise to SCK Rise
Hold Time
Note 1: TUE is specified with no resistive load.
Note 2: Guaranteed by design.
Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC.
Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, IDD decreases slightly.
Note 5: All input signals are specified with tR = tF
≤ 5ns. Logic input swing is 0 to 5V.
Note 6: Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO
pin has an internal active pullup.)
Note 7: Serial data clocked out of SDO on SCK’s rising edge.
Note 8: SDO changes from High-Z state to 90% of final value.
Note 9: SDO rises 10% toward High-Z state.
TIMING CHARACTERISTICS (Note 5)
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MAX537BCPE 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
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