參數(shù)資料
型號: MAX537ACPE+
廠商: Maxim Integrated Products
文件頁數(shù): 13/24頁
文件大?。?/td> 0K
描述: IC DAC 12BIT QUAD CALIB 16-DIP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 25
設(shè)置時間: 3µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 雙 ±
功率耗散(最大): 842mW
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 16-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 16-PDIP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): *
MAX536/MAX537
SS is an input intended for use in a multimaster environ-
ment. However, SS or unused PORT D bit RXD, TXD, or
possibly MISO (if DAC readback is not used) should be
configured as a general-purpose output and used as CS by
setting the appropriate Data Direction Register bit.
The SPCR configuration (memory location $1028) is shown
below:
When MSTR = 1 in the SPCR, a write to the Serial
Peripheral Data I/O Register (SPDR), located at memory
location $102A, initiates the transmission/reception of
data. The data transfer is monitored and the appropri-
ate flags are set in the Serial Peripheral Status
Register (SPSR).
The SPSR configuration is shown below:
An example of 68HC11 programming code for a
two-byte SPI transfer to the MAX536/MAX537 is given in
Table 4. SS is used for CS, the high byte of MAX536/
MAX537 digital data is stored in memory location $0100,
and the low byte is stored in memory location $0101.
Interfacing to Other Controllers
When using MICROWIRE, refer to the section on Inter-
facing to the M68HC11 for guidance, since MICROWIRE
can be considered similar to SPI when CPOL = 0 and
CPHA = 0. When interfacing to Intel’s 80C51/80C31
microcontroller family, use bit-pushing to configure a
desired port as the MAX536/MAX537 interface port. Bit-
pushing involves arbitrarily assigning I/O port bits as
interface control lines, and then writing to the port each
time a signal transition is required.
Unipolar Output
For a unipolar output, the output voltages and the reference
inputs are the same polarity. Figure 10 shows the
MAX536/MAX537 unipolar output circuit, which is also the typ-
ical operating circuit. Table 5 lists the unipolar output codes.
Bipolar Output
The MAX536/MAX537 outputs can be configured for
bipolar operation using Figure 11’s circuit. One op amp
and two resistors are required per DAC. With R1 = R2:
VOUT = VREF [(2NB/4096) - 1]
where NB is the numeric value of the DAC’s binary input
code. Table 6 shows digital codes and corresponding
output voltages for Figure 11’s circuit.
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
20
______________________________________________________________________________________
DAC CONTENTS
ANALOG OUTPUT
MSB
LSB
4095
1111
+VREF ( ——— )
4096
2049
1000
0000
0001
+VREF ( ——— )
4096
2048
+VREF
1000
0000
+VREF ( ——— ) = ————
4096
2
2047
0111
1111
+VREF ( ——— )
4096
1
0000
0001
+VREF ( ——— )
4096
0000
0V
DAC CONTENTS
ANALOG OUTPUT
MSB
LSB
2047
1111
+VREF ( ——— )
2048
1
1000
0000
0001
+VREF ( ——— )
2048
1000
0000
0V
1
0111
1111
-VREF ( ——— )
2048
2047
0000
0001
-VREF ( ——— )
2048
0000
-VREF ( ——— ) = -VREF
2048
Table 5. Unipolar Code Table
Table 6. Bipolar Code Table
NOTE: 1 LSB = (VREF) (
4096
)
1
BIT
7
6
543210
NAME
SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0
SETTING AFTER RESET
00
0
1
U
*
U
*
SETTING FOR TYPICAL SPI COMMUNICATION
0
1
0100
0
**
1
**
*U = Unknown
**Depends on P clock frequency.
Always configure the 68HC11 as the “master” controller
and the MAX536/MAX537 as the “slave” device.
BIT
76
5
4
3
2
1
0
NAME
SPIF WCOL
MODF
RESET CONDITIONS
00
0
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