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參數(shù)資料
| 型號(hào)： | MAX536AEWE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | DAC |
| 英文描述： | LJT 37C 37#22D SKT PLUG |
| 中文描述： | QUAD, SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO16 |
| 封裝： | 0.300 INCH, MS-013AA, SOIC-16 |
| 文件頁(yè)數(shù)： | 4/24頁(yè) |
| 文件大小： | 361K |
| 代理商： | MAX536AEWE |
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M
Calibrated, Quad, 12-Bit
Voltage-Output DACs with S erial Interfac e
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX536 (continued)
(V
DD
= +15V, V
SS
= -5V, REFAB/REFCD = 10V, AGND = DGND = 0V, R
L
= 5k
, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
TIMING CHARACTERISTICS
(Note 5)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
t
POR
20
μ
s
SCK Clock Period
SCK Pulse Width High
SCK Pulse Width Low
t
CP
t
CH
t
CL
100
30
30
ns
ns
ns
t
CSS
20
ns
t
CSH
10
ns
SDI Setup Time
SDI Hold Time
t
DS
t
DH
40
0
26
ns
ns
t
DO1
1k
pull-up on SDO
to V
DD,
C
LOAD
= 50pF
1k
pull-up on SDO
to V
DD,
C
LOAD
= 50pF
SDO high
SDO low
SDO high
SDO low
78
50
81
53
105
80
110
85
ns
SCK Fall to SDO Valid
Propagation Delay (Note 7)
t
DO2
ns
t
DV
27
45
ns
t
TR
40
60
ns
SCK Rise to
CS
Fall Delay
CS
Rise to SCK Rise
Hold Time
t
CS0
Continuous SCK, SCK edge ignored
20
ns
t
CS1
SCK edge ignored
20
ns
LDAC
Pulse Width Low
CS
Pulse Width High
t
LDAC
t
CSW
30
40
ns
ns
Internal Power-On Reset
Pulse Width (Note 2)
CS
Fall to SCK Rise
Setup Time
SCK Rise to
CS
Rise
Hold Time
SCK Rise to SDO Valid
Propagation Delay (Note 6)
CS
Fall to SDO Enable
(Note 8)
CS
Rise to SDO Disable
(Note 9)
Note 1:
TUE is specified with no resistive load.
Note 2:
Guaranteed by design.
Note 3:
Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC.
Note 4:
Digital inputs at 2.4V; with digital inputs at CMOS levels, I
DD
decreases slightly.
Note 5:
All input signals are specified with t
R
= t
F
≤
5ns. Logic input swing is 0V to 5V.
Note 6:
Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO
pin has an internal active pull-up.)
Note 7:
Serial data clocked out of SDO on SCK’s rising edge.
Note 8:
SDO changes from High-Z state to 90% of final value.
Note 9:
SDO rises 10% toward High-Z state.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MAX536AEWE+ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit 4Ch Precision DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX536AEWE+T | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit 4Ch Precision DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX536AEWE-T | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX536AMDE | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX536ASH | 制造商:Maxim Integrated Products 功能描述:536ASH |
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