參數(shù)資料
型號(hào): MAX5362NEUK+T
廠商: Maxim Integrated Products
文件頁數(shù): 13/13頁
文件大小: 0K
描述: IC DAC 6BIT LP 2WIRE SER SOT23-5
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時(shí)間: 20µs
位數(shù): 6
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 571mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SC-74A,SOT-753
供應(yīng)商設(shè)備封裝: SOT-23-5
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極
采樣率(每秒): *
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
_______________________________________________________________________________________
9
Power-On Reset
The MAX5360/MAX5361/MAX5362 have a power-on
reset circuit to set the DAC’s output to 0 when VDD is
first applied or when VDD dips below 1.7V. This ensures
that unwanted DAC output voltages will not occur
immediately following a system startup, such as after a
loss of power. The output glitch on startup is typically
<50mV.
Shutdown Mode
The MAX5360/MAX5361/MAX5362 include a software-
controlled shutdown mode that reduces the supply cur-
rent to <1A. All internal circuitry is disabled and an
internal 10k
Ω resistor is placed from OUT to GND to
ensure 0V at OUT while in shutdown. The device enters
shutdown in less than 5s and exits shutdown in less
than 50s.
Digital Section
Serial interface
The MAX5360/MAX5361/MAX5362 use a simple two-
wire serial interface requiring only two I/O lines (two-
wire bus) of a standard microprocessor (P) port.
Figure 3 shows the timing diagram for signals on the 2-
wire bus.
The two bus lines (SDA and SCL) must be high when
the bus is not in use. The MAX5360/MAX5361/
MAX5362 are receive-only devices (slaves) and must
be controlled by a bus master device. Figure 4 shows a
typical application where multiple devices can be con-
nected to the bus provided they have different address
settings. External pullup resistors are not necessary on
these lines (when driven by push-pull drivers), though
the MAX5360/MAX5361/MAX5362 can be used in
applications where pullup resistors are required (such
as in I2C systems) to maintain compatibility with exist-
ing circuitry. The serial interface operates at SCL rates
up to 400kHz. The SDA state is allowed to change only
while SCL is low, with the exception of START and
STOP conditions as shown in Figure 5. Each transmis-
sion consists of a START condition sent by the bus
master device, followed by the MAX5360/MAX5361/
MAX5362’s preset slave address, a power-mode bit,
the DAC data (6 bits + 2 subbits), and finally, a STOP
SCL
SDA
tLOW
tHIGH
tF
tR
tHD, STA
tHD, DAT
tHD, STA
tSU, DAT
tSU, STA
tBUF
tSU, STO
START CONDITION
STOP CONDITION
REPEATED START CONDITION
START CONDITION
Figure 3. Two-Wire Serial Interface Timing Diagram
μC
SDA
SCL
RS*
VDD
OFFSET ADJUSTMENT
THRESHOLD ADJUSTMENT
GAIN ADJUSTMENT
RS* IS OPTIONAL.
SCL
SDA
VDD
OUT
MAX5360M
2V REFERENCE
SCL
SDA
VDD
OUT
MAX5361N
4V REFERENCE
SCL
SDA
VDD
OUT
MAX5362P
VDD REFERENCE
Figure 4. Typical Application Circuit
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