參數(shù)資料
型號: MAX534BCPE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: +5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
中文描述: SERIAL INPUT LOADING, 8 us SETTLING TIME, 8-BIT DAC, PDIP16
封裝: 0.300 INCH, PLASTIC, DIP-16
文件頁數(shù): 6/16頁
文件大?。?/td> 125K
代理商: MAX534BCPE
M
6
_______________________________________________________________________________________
______________________________________________________________Pin Desc ription
PIN
DAC B Voltage Output
DAC A Voltage Output
Reference-Voltage Input
OUTB
OUTA
REF
1
2
3
FUNCTION
NAME
Software-Programmable Logic Output
Power-Down Enable. Must be high to allow software shutdown mode.
UPO
PDE
4
5
Load DAC Input (active low). Driving this asynchronous input low (level sensitive) transfers the contents
of each input latch to its respective DAC latch.
Clear DAC Input (active low). Driving
CLR
low asynchronously clears the input and DAC registers, and
sets all DAC outputs to zero.
LDAC
6
Serial Data Output. Sinks and sources current. Data at DOUT can be clocked out on the rising or falling
edge of SCLK (Table 1).
Chip-Select Input (active low). Data is shifted in and out when
CS
is low. Programming commands are
executed when
CS
returns high.
DOUT
8
CLR
7
Serial Clock Input. Data is clocked in on the rising edge and clocked out on the falling (default) or rising
edge (A0 = A1 = 1, see Table 1).
Serial Data Input. Data is clocked in on the rising edge of SCLK.
SCLK
10
Digital Ground
Power Supply, +4.5V to +5.5V
DGND
V
DD
12
13
DIN
11
Analog Ground
DAC D Voltage Output
AGND
OUTD
14
15
DAC C Voltage Output
OUTC
16
CS
9
+5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
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