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參數(shù)資料
| 型號： | MAX533 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Single Universal Serial Bus Port Transient Suppressor 4-DSBGA -40 to 85 |
| 中文描述： | 2.7V、低功耗、8位四路DAC，帶有滿擺幅輸出緩沖器 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 146K |
| 代理商： | MAX533 |
M
2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS (continued)
(V
DD
= +2.7V to +3.6V, V
REF
= 2.5V, AGND = DGND = 0V, C
DOUT
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Typical values are at V
DD
= +3V and T
A
= +25°C.)
Note 1:
INL and DNL are measured with R
L
referenced to ground. Nonlinearity is measured from the first code that is greater than
or equal to the maximum offset specification to code FF hex (full scale). See DAC Linearity and Voltage Offsetsection.
V
REF
= 2.5Vp-p, 10kHz. Channel-to-channel isolation is measured by setting one DAC’s code to FF hex and setting all
other DAC’s codes to 00 hex.
V
REF
= 2.5Vp-p, 10kHz. DAC code = 00 hex.
Guaranteed by design, not production tested.
Output settling time is measured from the 50% point of the rising edge of
CS
to 1/2LSB of V
OUT
’s final value.
Digital crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other
DAC.
If
LDAC
is activated prior to
CS
’s rising edge, it must stay low for t
LDAC
or longer after
CS
goes high.
When DOUT is not used. If DOUT is used, f
CLK
max is 4MHz, due to the SCLK to DOUT propagation delay.
Serial data clocked out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of V
DD
).
Note 10:
Serial data clocked out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of V
DD
).
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
CS
Rise to SCLK Rise Setup
Time
t
CS1
50
ns
SCLK Rise to
CS
Fall Delay
t
CS0
50
40
ns
MAX533M
MAX533C/E
MAX533M
40
MAX533C/E
SCLK Fall to DOUT Valid
Propagation Delay (Note 10)
t
DO2
250
ns
MAX533M
210
MAX533C/E
SCLK Rise to DOUT Valid
Propagation Delay (Note 9)
t
DO1
230
ns
MAX533M
200
MAX533C/E
40
50
CS
Fall to SCLK Rise Setup
Time
t
CSS
40
50
ns
SCLK Pulse Width Low
t
CL
ns
MAX533C/E
MAX533M
MAX533C/E
MAX533M
40
50
SCLK Pulse Width High
t
CH
ns
MAX533C/E
MAX533M
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
SERIAL-INTERFACE TIMING
10
8.3
SCLK Clock Frequency (Note 8)
f
CLK
MHz
SCLK Rise to
CS
Rise Hold Time
t
CSH
0
ns
40
50
0
DIN to SCLK Rise to Setup Time
t
DS
DIN to SCLK Rise to Hold Time
t
DH
ns
CONDITIONS
MAX533C/E
MAX533M
MAX533C/E
MAX533M
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