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參數(shù)資料
| 型號(hào)： | MAX532AEWE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MDAC 12BIT DUAL SER 16-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 2.5µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 762mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | * |
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL = 2k, CL = 100pF,
VOUT_ connected to RFB_, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SYMBOL
VREF = 100mVp-p sine wave;
DAC latch loaded with all 1s
1.0
MHz
VREF = 20Vp-p 10kHz sine wave;
DAC latch loaded with all 0s
-77
dB
Full-Power Bandwidth
125
kHz
THD
Total Harmonic Distortion
-90
dB
Output Noise Voltage
0.1Hz to 10Hz
2
VRMS
Digital Crosstalk
DACA code all 1s, DACB code transition from all 0s to all 1s
10
nV-s
Digital Feedthrough
CS = 1; transitions on SCLK, LDAC, DIN
1.1
nV-s
PARAMETER
tCL
CONDITIONS
MIN
TYP
MAX
SCLK Pulse Width Low
UNITS
SYMBOL
fCLK
tCH
80
ns
tDS
50
ns
tCSS1
CS Rise to SCLK Rise Setup Time
SCLK Clock Frequency
50
ns
tCSS0
CS Fall to SCLK Rise Setup Time
6.25
MHz
50
ns
tDH
DIN to SCLK Rise Hold Time
0
ns
SCLK Pulse Width High
80
ns
Multiplying Feedthrough
Error
Unity-Gain Small-Signal
Bandwidth
VREF = 20Vp-p sine wave;
DAC latch loaded with all 1s
VREF = 6VRMS, 1kHz sine wave;
DAC latch loaded with all 1s
Note 1: Static performance tested at VDD = +15V, VSS = -15V. Performance over supplies guaranteed by PSR test.
Note 2: Guaranteed by design. Not subject to production testing.
Note 3: Open-drain output.
TIMING CHARACTERISTICS
(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V) (Notes 4, 5)
tCSH0
SCLK Fall to
CS Fall Hold Time
5
ns
tCSH1
SCLK Rise to
CS Rise Hold Time
80
ns
tCSW
CS Pulse Width High
120
ns
tDO
SCLK Fall to DOUT Valid (Note 6)
CL = 20pF, RPULL-UP = 1k to 5V
0
200
ns
tDV
CS Fall to DOUT Enable (Note 7)
CL = 20pF, RPULL-UP = 1k to 5V
100
ns
tTR
CS Rise to DOUT Disable (Note 7)
CL = 20pF, RPULL-UP = 1k to 5V
60
ns
tLDAC
LDAC Pulse Width Low
60
ns
tLDACS
CS Rise to LDAC Fall Setup Time
100
ns
DIN to SCLK Rise Setup Time
Note 4: All input signals are specified with tR = tF ≤ 5ns. Logic input swing is 0V to 5V.
Note 5: See Figure 1.
Note 6: Timing is for SCLK fall to DOUT fall to 0.8V, or for SCLK fall to DOUT rise to 2.4V. Additional time must be added for any
larger passive RC pull-up delay.
Note 7: DOUT enable: DOUT falls to 4.5V from 5.0V. DOUT disable: DOUT rises to 0.5V from 0V.
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