參數(shù)資料
型號: MAX5302CUA+T
廠商: Maxim Integrated Products
文件頁數(shù): 6/12頁
文件大?。?/td> 0K
描述: IC DAC 12BIT LP SERIAL 8-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時間: 14µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): *
MAX5302
Low-Power, 12-Bit Voltage-Output DAC
with Serial Interface
_______________________________________________________________________________________
3
(Note 3)
CS = VDD, DIN = 100kHz
Rail-to-rail (Note 2)
To ±1/2LSB, VSTEP = 2.5V
CONDITIONS
mA
0.28
0.4
IDD
Supply Current
V
4.5
5.5
VDD
Supply Voltage
nVs
5
Digital Feedthrough
s
20
Start-Up Time
A
0.001
±0.1
Current into FB
V
0 to VDD
Output Voltage Swing
s
14
Output Settling Time
V/s
0.6
SR
Voltage Output Slew Rate
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
(Note 3)
A
420
Supply Current in Shutdown
A
0.001
±0.5
Reference Current in Shutdown
ns
40
tCH
SCLK Pulse Width High
ns
100
tCP
SCLK Clock Period
ns
40
tCSS
CS Fall to SCLK Rise Setup Time
ns
40
tDS
DIN Setup Time
ns
0
tCSH
SCLK Rise to CS Rise Hold Time
ns
40
tCL
SCLK Pulse Width Low
ns
40
tCS1
CS Rise to SCLK Rise Hold Time
ns
100
tCSW
CS Pulse Width High
ns
40
tCS0
SCLK Rise to CS Fall Delay
ns
0
tDH
DIN Hold Time
Note 1: Guaranteed from code 11 to code 4095 in unity-gain configuration.
Note 2: Accuracy is better than 1LSB for VOUT = 8mV to (VDD - 100mV), guaranteed by a power-supply rejection test at the end
points.
Note 3: RL =
∞, digital inputs at GND or VDD.
DIGITAL INPUTS
DYNAMIC PERFORMANCE
POWER SUPPLIES
TIMING CHARACTERISTICS (Figure 6)
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 8, VDD = +5V ±10%, VREF = +2.5V, RL = 5k
, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical val-
ues are at TA = +25°C. Output buffer connected in unity-gain configuration.)
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