參數(shù)資料
型號: MAX525AEPP+
廠商: Maxim Integrated Products
文件頁數(shù): 7/16頁
文件大小: 0K
描述: IC DAC 12BIT QUAD LP 20-DIP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 18
設(shè)置時間: 12µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 20-DIP(0.300",7.62mm)
供應商設(shè)備封裝: 20-PDIP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): *
Power-Supply Considerations
On power-up, all input and DAC registers are cleared
(set to zero code) and DOUT is in Mode 0 (serial data
is shifted out of DOUT on the clock’s falling edge).
For rated MAX525 performance, limit REFAB/REFCD to
less than 1.4V below VDD. Bypass VDD with a 4.7F
capacitor in parallel with a 0.1F capacitor to AGND.
Use short lead lengths and place the bypass capaci-
tors as close to the supply pins as possible.
Grounding and Layout Considerations
Digital or AC transient signals between AGND and
DGND can create noise at the analog outputs. Tie
AGND and DGND together at the DAC, then tie this
point to the highest-quality ground available.
Good printed circuit board ground layout minimizes
crosstalk between DAC outputs, reference inputs, and
digital inputs. Reduce crosstalk by keeping analog
lines away from digital lines. Wire-wrapped boards are
not recommended.
MAX525
Low-Power, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
______________________________________________________________________________________
15
DAC_
MAX525
REF_
OUT_
R
IOUT
2N3904
VL
FB_
Figure 13. Digitally Programmable Current Source
__________________Pin Configuration
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
VDD
FBD
OUTD
OUTC
OUTB
OUTA
FBA
AGND
TOP VIEW
FBC
REFCD
PDL
UPO
CS
CL
REFAB
FBB
12
11
9
10
DOUT
DGND
SCLK
DIN
DIP/SSOP
MAX525
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