參數(shù)資料
型號: MAX5253ACAP+T
廠商: Maxim Integrated Products
文件頁數(shù): 3/16頁
文件大?。?/td> 0K
描述: IC DAC 12BIT QUAD 3V 20-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,000
設(shè)置時間: 16µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): *
Power-Down Lockout (PDL)
The power-down lockout pin PDL disables software
shutdown when low. When in shutdown, transitioning
PDL from high to low wakes up the part with the output
set to the state prior to shutdown. PDL could also be
used to asynchronously wake up the device.
Daisy-Chaining Devices
Any number of MAX5253s can be daisy chained by
connecting the DOUT pin of one device to the DIN pin
of the following device in the chain (Figure 7).
Since the MAX5253’s DOUT pin has an internal active
pull-up, the DOUT sink/source capability determines
the time required to discharge/charge a capacitive
load. Refer to the serial-data-out VOH and VOL specifi-
cations in the Electrical Characteristics.
Figure 8 shows an alternate method of connecting sev-
eral MAX5253s. In this configuration, the data bus is
common to all devices; data is not shifted through a
daisy chain. More I/O lines are required in this configu-
ration because a dedicated chip-select input (CS) is
required for each IC.
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
______________________________________________________________________________________
11
CS
SCLK
DIN
DOUT
(MODE 1)
MSB FROM
PREVIOUS WRITE
MSB FROM
PREVIOUS WRITE
COMMAND
EXECUTED
9
8
16
1
A0
A1
D0
C1
C0
D11 D10
D9
D6
D5
D4
D3
D2
D1
D8
D7
DOUT
(MODE 0)
A0
A1
D0
A1
C1
C0
D11 D10
D9
D6
D5
D4
D3
D2
D1
D8
D7
A0
A1
D0
A1
C1
C0
D11 D10
D9
D6
D5
D4
D3
D2
D1
D8
D7
DATA PACKET (N)
DATA PACKET (N-1)
DATA PACKET (N)
DATA PACKET (N-1)
DATA PACKET (N)
Figure 5. Serial-Interface Timing Diagram
SCLK
DIN
DOUT
tCSO
tCSS
tCL
tCH
tCP
tDO1
tCSW
tCS1
tDO2
tCSH
tDS
tDH
CS
Figure 6. Detailed Serial-Interface Timing Diagram
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