參數(shù)資料
型號(hào): MAX5237EUB+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 15/19頁(yè)
文件大?。?/td> 0K
描述: IC DAC 10BIT DUAL 5V 10-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時(shí)間: 10µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 帶卷 (TR)
輸出數(shù)目和類(lèi)型: 2 電壓,單極;2 電壓,雙極
采樣率(每秒): *
MAX5236/MAX5237
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 10-Bit DACs
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS—MAX5236 (continued)
(VDD = +2.7V to +3.6V, GND = 0, VREFA = VREFB = +1.25V, RL = 5k
, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Time Required for Output to Settle
After Turning on VDD
(Note 7)
60
s
Time Required for Output to
Settle After Exiting Full Power-
Down
(Note 7)
60
s
Time Required for Output to
Settle After Exiting DAC Power-
Down
(Note 7)
50
s
Digital Feedthrough
CS = VDD, fSCLK = 100kHz, VSCLK = 3VP-P
5
nV-s
Major Carry Glitch Energy
115
nV-s
POWER SUPPLIES
Power-Supply Voltage
VDD
2.7
3.6
V
Power-Supply Current
IDD
(Note 8)
325
430
A
Full power-down mode
0.4
5
One DAC shutdown mode
175
200
Power-Supply Current in Power-
Down and Shutdown Modes
ISHDN
Both DACs shutdown mode
25
40
A
TIMING CHARACTERISTICS—MAX5237 (FIGURES 1 AND 2)
(VDD = +4.5V to +5.5V, GND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Clock Period
tCP
74
ns
SCLK Pulse Width High
tCH
30
ns
SCLK Pulse Width Low
tCL
30
ns
CS Fall to SCLK Rise Setup Time
tCSS
30
ns
SCLK Rise to CS Rise Hold Time
tCSH
0ns
DIN Setup Time
tDS
30
ns
DIN Hold Time
tDH
0ns
SCLK Rise to CS Fall Delay
tCS0
10
ns
CS Rise to SCLK Rise Hold Time
tCS1
30
ns
CS Pulse Width High
tCSW
75
ns
LDAC Pulse Width Low
tLDL
30
ns
CS Rise to LDAC Rise Hold Time
tCSLD
(Note 9)
40
ns
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