參數(shù)資料
型號(hào): MAX5233EEE+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 15/18頁(yè)
文件大?。?/td> 0K
描述: IC DAC 10BIT DUAL 5V SER 16-QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時(shí)間: 10µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類(lèi)型: 2 電壓,單極
采樣率(每秒): *
MAX5232/MAX5233
3V/5V, 10-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS—MAX5232
(VDD = +2.7V to +3.6V, VAGND = VDGND = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
(Figures 1 and 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Clock Period
tCP
74
ns
SCLK Pulse Width High
tCH
30
ns
SCLK Pulse Width Low
tCL
30
ns
CS Fall to SCLK Rise Setup Time
tCSS
30
ns
SCLK Rise to
CS Rise Hold Time
tCSH
0ns
DIN Setup Time
tDS
30
ns
DIN Hold Time
tDH
0ns
CLOAD = 200pF
60
200
SCLK Rise to DOUT Valid
Propagation Delay Time
tDO1
CLOAD = 100pF
45
ns
CLOAD = 200pF
60
200
SCLK Fall to DOUT Valid
Propagation Delay Time
tDO2
CLOAD = 100pF
45
ns
SCLK Rise to
CS Fall Delay
tCS0
10
ns
CS Rise to SCLK Rise Hold Time
tCS1
30
ns
CS Pulse Width High
tCSW
75
ns
LDAC Pulse Width Low
tLDL
30
ns
CS Rise to LDAC Rise Hold Time
tCSLD
(Note 8)
75
ns
Note 8: This timing requirement applies only to
CS rising edges, which execute commands modifying the DAC input register
contents.
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (MAX5232)
MAX5232/MAX5233
toc01
DIGITAL INPUT CODE
INL
(LSB)
1000
875
750
625
500
375
250
125
0
-0.050
-0.025
0
0.025
0.050
0.075
-0.075
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (MAX5233)
MAX5232/MAX5233
toc02
DIGITAL INPUT CODE
INL
(LSB)
1000
875
750
625
500
375
250
125
0
-0.050
-0.025
0
0.025
0.050
0.075
-0.075
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (MAX5232)
MAX5232/MAX5233
toc03
DIGITAL INPUT CODE
DNL
(LSB)
1000
875
750
625
500
375
250
125
0
-0.050
0
0.025
0.050
-0.025
Typical Operating Characteristics
(VDD = +3V (MAX5232), VDD = +5V (MAX5233), RL = 5k, CL = 100pF, OS_ = AGND, both DACs enabled with full-scale output code,
TA = +25°C, unless otherwise noted.)
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