參數(shù)資料
型號(hào): MAX5232EEE+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 2/18頁(yè)
文件大?。?/td> 0K
描述: IC DAC 10BIT DUAL 3V SER 16-QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時(shí)間: 10µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電壓,單極
采樣率(每秒): *
MAX5232/MAX5233
3V/5V, 10-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
10
______________________________________________________________________________________
PIN
NAME
FUNCTION
1
OSA
DAC A Offset Adjust
2
OUTA
DAC A Output
3
RSTV
Reset Value Input
1: Connect to VDD to select midscale as the reset value.
0: Connect to DGND to select zero as the reset value.
4
LDAC
Load DACs A and B
5
CLR
Clear Input. Both DAC outputs go to zero or midscale. Clears both DAC internal registers (input
register and DAC register) to its predetermined (RSTV) state.
6
CS
Chip-Select Input
7
DIN
Serial Data Input. Data is clocked in on the rising edge of SCLK.
8
SCLK
Serial Clock Input
9
DGND
Digital Ground
10
DOUT
Serial Data Output
11
PDL
Power-Down Lockout. Disables shutdown of both DACs when low.
12
REF
Reference Output. Reference provides a 2.465V (MAX5233) or 1.234V (MAX5232) nominal output.
13
AGND
Analog Ground
14
VDD
Positive Power Supply. Bypass VDD with a 0.1F capacitor in parallel with a 4.7F capacitor to
AGND, and bypass VDD with a 0.1F capacitor to DGND.
15
OUTB
DAC B Output
16
OSB
DAC B Offset Adjust
Pin Description
CS
SCLK
DIN
COMMAND EXECUTED
9
8
16
(1)
1
C1
C2
S0
C0
D9
D8
D7
D6
D3
D2
D1
D0
S2
(MODE 0)
(MODE 1)
DOUT
C2
C1
C2
C1
S1
D5
D4
Figure 1. Serial Interface Timing
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