參數(shù)資料
型號: MAX5204AEUB+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/13頁
文件大?。?/td> 0K
描述: IC DAC 16BIT SRL 10UMAX
標準包裝: 2,500
設置時間: 25µs
位數(shù): 16
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 444.4mW
工作溫度: -40°C ~ 105°C
安裝類型: *
封裝/外殼: *
供應商設備封裝: *
包裝: *
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in MAX
10
______________________________________________________________________________________
Applications Information
Power Supply and Bypassing
Considerations
Bypass the power supply with a 10F capacitor in par-
allel with a 0.1F capacitor to AGND. Minimize lead
lengths to reduce lead inductance. If noise becomes
an issue, use shielding and/or ferrite beads to increase
isolation.
Output Buffer
The MAX5204–MAX5207 include low-offset, low-noise
buffers enabling the output to source 15mA or sink
5mA. The output buffer operates at a slew rate of
0.6V/s. With a 1/4 FS to 3/4 FS output transition, the
buffer output typically settles to 1LSB in about 25s.
The MAX5204–MAX5207 output buffers provide a low
0.2
typical output impedance. The MAX5204–
MAX5207 buffer amplifiers typically produce
120nV/
√Hz noise at 10kHz.
tCS0L
tCSWL
tCSWH
SHUTDOWN
WAKE-UP
tCS0L
tCSWL
tCSWH
SHUTDOWN
WAKE-UP
SCLK
CS
A. WAKING UP USING A THIRD FALLING EDGE ON CS.
B. WAKING UP USING A TRANSITION ON SCLK.
SCLK
CS
Figure 4. Shutdown Timing
tCL
tCH
tCSS
D14
D15
tDS
tDH
D0
tCSH
tCS1
tCS0
SCLK
CS
DIN
LDAC
tCP
tCSWH
tLDACS
tLDAC
Figure 3. 4-Wire Interface Timing Diagram
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