參數(shù)資料
型號: MAX5187BEEG+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/15頁
文件大小: 0K
描述: IC DAC 8BIT 40MHZ 24-QSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
設置時間: 25µs
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 24-QSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): *
MAX5187/MAX5190
8-Bit, 40MHz, Current/Voltage-Output DACs
10
______________________________________________________________________________________
PD
(POWER-DOWN SELECT)
DACEN
(DAC ENABLE)
POWER-DOWN MODE
OUTPUT STATE
0
Standby
MAX5187
High-Z
MAX5190
AGND
0
1
Wake-Up
Last state prior to standby mode
1
X
Shutdown
MAX5187
High-Z
MAX5190
AGND
Table 1. Power-Down Mode Selection
X = Don’t care
External Reference
To disable the MAX5187/MAX5190’s internal reference,
connect REN to DVDD. A temperature-stable external ref-
erence may now be applied to drive the REFO pin to set
the full-scale output (Figure 3). Choose a reference that
can supply at least 150A to drive the bias circuit that
generates the cascode current for the current array. For
improved accuracy and drift performance, choose a volt-
age reference with a fixed output voltage, such as the
+1.2V, 25ppm/°C MAX6520 bandgap reference.
Standby Mode
To enter the lower power standby mode, connect the
digital inputs PD and DACEN to DGND. In standby,
both the reference and the control amplifier are active
with the current array inactive. To exit this condition,
DACEN must be pulled high with PD held at DGND.
Both the MAX5187 and MAX5190 typically require 50s
to wake up and allow both the outputs and the refer-
ence to settle.
Shutdown Mode
For lowest power consumption, the MAX5187/MAX5190
provide a power-down mode in which the reference,
control amplifier, and current array are inactive and the
DAC’s supply current is reduced to 1A. To enter this
mode, connect PD to DVDD. To return to active mode,
connect PD to DGND and DACEN to DVDD. About 50s
are required for the parts to leave shutdown mode and
settle to their outputs’ values prior to shutdown.
Timing Information
Figure 4 shows a detailed timing diagram for the
MAX5187/MAX5190. With each high transition of the
clock, the input latch is loaded with the digital value set
by bits D7 through D0. The content of the input latch is
then shifted to the DAC register, and the output
updates at the rising edge of the next clock.
CLK
D0–D7
OUT
N - 1
N
N + 1
tDS
tDH
tCH
tCL
tCLK
Figure 4. Timing Diagram
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相關代理商/技術參數(shù)
參數(shù)描述
MAX5188 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Dual, 8-Bit, 40MHz, Current/Voltage, Alternate-Phase Output DACs
MAX5188_01 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Dual, 8-Bit, 40MHz, Current/Voltage,Alternate-Phase Output DACs
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