參數(shù)資料
型號(hào): MAX5181BEEG+T
廠商: Maxim Integrated Products
文件頁數(shù): 16/16頁
文件大小: 0K
描述: IC DAC 10BIT DUAL 40MHZ 24-QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時(shí)間: 25µs
位數(shù): 10
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-QSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): *
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
_______________________________________________________________________________________
9
reference output-current resistor (RSET = 9.6k
Ω) sets
IREF to 125A and IFS to 1mA.
External Reference
To disable the MAX5181/MAX5184’s internal reference,
connect
REN to DVDD. A temperature-stable, external
reference may now be applied to drive the REFO pin to
set the full-scale output (Figure 3). Choose a reference
capable of supplying at least 150A to drive the bias
circuit that generates the cascode current for the cur-
rent array. For improved accuracy and drift perfor-
mance, choose a fixed output voltage reference such
as the 1.2V, 25ppm/°C MAX6520 bandgap reference.
Standby Mode
To enter the lower-power standby mode, connect digital
inputs PD and DACEN to DGND. In standby, both the
reference and the control amplifier are active with the
current array inactive. To exit this condition, DACEN
must be pulled high with PD held at DGND. The
MAX5181/MAX5184 typically require 50s to wake up
and let both outputs and the reference settle.
Shutdown Mode
For lowest power consumption, the MAX5181/MAX5184
provide a power-down mode in which the reference, con-
trol amplifier, and current array are inactive and the DAC
supply current is reduced to 1A. To enter this mode,
connect PD to DVDD. To return to active mode, connect
PD to DGND and DACEN to DVDD. About 50s are
required for the parts to leave shutdown mode and settle
to their outputs’ values prior to shutdown. Table 1 lists the
power-down mode selection.
Timing Information
Figure 4 shows a detailed timing diagram for the
MAX5181/MAX5184. With each high transition of the
clock, the input latch is loaded with the digital value set
by bits D9 through D0. The content of the input latch is
then shifted to the DAC register, and the output up-
dates at the rising edge of the next clock.
Outputs
The MAX5181 output is designed to supply full-scale
output currents of 1mA into 400
Ω loads in parallel with
a capacitive load of 5pF. The MAX5184 features inte-
grated 400
Ω resistors that restore the array current to
proportional, differential voltages of 400mV. These dif-
ferential output voltages can then be used to drive a
balun transformer or a low-distortion, high-speed oper-
ational amplifier to convert the differential voltage into a
single-ended voltage.
RSET**
9.6k
Ω
IFS
RSET
CCOMP*
REFR
AGND
DGND
IREF
REFO
MAX4040
RSET
1.2V
BANDGAP
REFERENCE
REN
CURRENT-
SOURCE ARRAY
*COMPENSATION CAPACITOR (CCOMP = 100nF)
**9.6k
ΩREFERENCE CURRENT-SET RESISTOR
INTERNAL TO MAX5184 ONLY. USE EXTERNAL
RSET FOR MAX5181.
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
MAX5181
MAX5184
Figure 2. Setting IFS with the Internal 1.2V Reference and the Control Amplifier
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參數(shù)描述
MAX5182 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Dual, 10-Bit, 40MHz Current/Voltage Alternate-Phase Output DACs
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