參數(shù)資料
型號(hào): MAX5123BEEE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: +5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/∑C Internal Reference
中文描述: SERIAL INPUT LOADING, 20 us SETTLING TIME, 12-BIT DAC, PDSO16
封裝: 0.150 INCH, 0.025 INCH PITCH, QSOP-16
文件頁(yè)數(shù): 5/20頁(yè)
文件大小: 285K
代理商: MAX5123BEEE
M
+5V /+3V, 12-Bit, S erial, Forc e/S ense DACs
with 10ppm/°C Internal Referenc e
_______________________________________________________________________________________
5
Note 1:
Accuracy is guaranteed by the following table:
Note 2:
Offset is measured at the code closest to 10mV.
Note 2:
The temperature coefficient is determined by the “box” method, in which the maximum
V
OUT
over the temperature range
is divided by
T and the typical reference voltage.
Note 4:
Accuracy is better than 1.0LSB for V
OUT
= 10mV to (V
DD
- 180mV). Guaranteed by PSR test on end points.
Note 5:
R
LOAD
=
and digital inputs are at either V
DD
or DGND.
TIMING CHARACTERISTICS—MAX5123 (+3V)
(V
DD
= +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ , internal reference, R
L
= 5k
, C
L
= 100pF, output amplifier connected
in unity-gain, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
ns
ns
ns
ns
60
0
60
0
t
CSS
t
CSH
t
DS
t
DH
CS
Fall to SCLK Rise Setup Time
SCLK Rise to
CS
Rise Hold Time
SDI Setup Time
SDI Hold Time
ns
150
ns
C
LOAD
= 200pF
75
t
CSW
t
CL
SCLK Pulse Width Low
CONDITIONS
ns
ns
150
75
t
CP
t
CH
SCLK Clock Period
SCLK Pulse Width High
CS
Pulse Width High
ns
75
t
CS1
CS
Rise to SCLK Rise Hold Time
C
LOAD
= 200pF
ns
200
t
DO1
SCLK Rise to DOUT Valid
Propagation Delay Time
ns
200
t
DO2
SCLK Fall to DOUT Valid
Propagation Delay Time
ns
10
t
CS0
SCLK Rise to
CS
Fall Delay Time
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
16
33
5
3
4095
4095
Accuracy Guaranteed
From Code:
To Code:
V
DD
(V)
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