參數(shù)資料
型號: MAX5122BEEE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: +5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/∑C Internal Reference
中文描述: SERIAL INPUT LOADING, 20 us SETTLING TIME, 12-BIT DAC, PDSO16
封裝: 0.150 INCH, 0.025 INCH PITCH, QSOP-16
文件頁數(shù): 11/20頁
文件大?。?/td> 285K
代理商: MAX5122BEEE
M
+5V /+3V, 12-Bit, S erial, Forc e/S ense DACs
with 10ppm/°C Internal Referenc e
______________________________________________________________________________________
11
The circuit in Figure 3 achieves a nominal reference
adjustment range of ±1%. Connect a 33nF capacitor
from REFADJ to AGND to establish low-noise DAC
operation. Larger capacitor values may be used, but
will result in increased start-up delay. The time constant
(
τ)
for the start-up delay is determined by the REFADJ
input impedance of 4k
and C
REFADJ
:
τ
= 4k
·
C
REFADJ
External Referenc e
An external reference may be applied to the REF pin.
Disable the internal reference by pulling REFADJ to
V
DD
. This allows an external reference signal (AC- or
DC-based) to be fed into the REF pin. For proper oper-
ation,
do not
exceed the input voltage range limits of 0
to (V
DD
- 1.4V) for V
REF
.
Determine the output voltage using the following equa-
tion (REFADJ = V
DD
):
V
OUT
= V
REF
[(NB / 4096) G]
where NB is the numeric value of the MAX5122/
MAX5123 input code (0 to 4095), V
REF
is the external
reference voltage, and G is the gain of the output
amplifier, set by an external resistor-divider. The REF
pin has a minimum input resistance of 40k
and is
code-dependent.
Output Amplifier
The MAX5122/MAX5123’s DAC output is internally
buffered by a precision amplifier with a typical slew rate
of 0.6V/μs. Access to the output amplifier’s inverting
input (FB) provides the user greater flexibility with
amplifier gain setting and signal conditioning (see
Applications Information.
The output amplifier typically settles to ±0.5LSB from a
full-scale transition within 20μs when it is connected in
unity gain and loaded with 5k
100pF. Loads less
than 1k
may result in degraded performance.
Power-Down Mode
These devices feature software- and hardware-pro-
grammable (PD pin) shutdown modes that reduce the
typical supply current to 3μA. To enter software shut-
down mode, program the control sequence for the DAC
as shown in Table 1.
In shutdown mode, the amplifier output becomes high-
impedance and the serial interface remains active.
Data in the input registers is saved, allowing the
MAX5122/MAX5123 to recall the output state prior to
entering shutdown when returning to normal operation.
To exit shutdown mode, load both input and DAC regis-
ters simultaneously or update the DAC register from the
input register. When returning from shutdown to normal
operation, wait 2ms for the reference to settle. When
using an external reference, the DAC requires only
20μs for the output to stabilize.
REFADJ
+3V
15k
100k
400k
33nF
MAX5123
REFADJ
+5V
90k
100k
400k
33nF
MAX5122
Figure 3a. MAX5122 Reference Adjust Circuit
Figure 3b. MAX5123 Reference Adjust Circuit
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