參數(shù)資料
型號: MAX5106EEE+
廠商: Maxim Integrated Products
文件頁數(shù): 6/19頁
文件大?。?/td> 0K
描述: IC DAC 8BIT QUAD NV 16-QSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 100
設置時間: 6µs
位數(shù): 8
數(shù)據(jù)接口: 串行
轉換器數(shù)目: 4
電壓電源: 單電源
功率耗散(最大): 666.7mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 16-QSOP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極
采樣率(每秒): *
產(chǎn)品目錄頁面: 1397 (CN2011-ZH PDF)
MAX5105/MAX5106
Nonvolatile, Quad, 8-Bit DACs
14
______________________________________________________________________________________
on the rising edge of CLK corresponding to D0. The
register write command does not affect data stored in
the nonvolatile memory. Figure 6 shows the register
write command timing diagram.
Nonvolatile Read Command
The nonvolatile read command makes the data from
the selected nonvolatile register available to external
devices. Data is clocked out on DOUT during the eight
clock cycles following A0. DOUT returns to a high-
impedance state when CS goes high. This command
has no effect on the DAC outputs, operating states, or
contents of the nonvolatile registers. Figure 7 shows the
nonvolatile read command timing diagram. RDY/BSY
remains high while a read is taking place.
D1
tCOS
D0
CS
CLK
DIN
START
C1
C0
DOUT
OUT_
D3
D2
A2
A0
D7
D6
D5
D4
A1
HIGH IMPEDANCE
AT VDD
(MAX5105 ONLY)
RDY/BSY
Figure 6. Register Write Command Timing Diagram
START
DIN
CLK
DOUT
A2
A0
A1
HIGH IMPEDANCE
D0
D1
D2
D4
D5
D6
D7
D3
AT VDD
(MAX5105 ONLY)
CI
CO
CS
RDY/BSY
Figure 7. Nonvolatile Read Command Timing Diagram
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