參數(shù)資料
型號(hào)： MAX5102BEUE+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 3/8頁(yè)
文件大小： 0K
描述： IC DAC 8BIT DUAL PAR-IN 16-TSSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
設(shè)置時(shí)間： 6µs
位數(shù)： 8
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 2 電壓，單極
采樣率（每秒）： *
MAX5102
+2.7V to +5.5V, Low-Power, Dual, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
_______________________________________________________________________________________
3
Note 1: Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded.
Note 2: Gain error is: [100 (VF0,meas - ZCE - VF0,ideal) / VREF]. Where VF0,meas is the DAC output voltage with input code F0 hex,
and VF0,ideal is the ideal DAC output voltage with input code F0 hex (i.e., VREF 240 / 256).
Note 3: Output settling time is measured from the 50% point of the falling edge of WR to ±1/2LSB of VOUT’s final value.
Note 4: Channel-to-channel isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any
other DAC output. The measured channel has a fixed code of 80 hex.
Note 5: Digital feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight
data inputs with WR at VDD.
Note 6: RL =
∞, digital inputs at GND or VDD.
Note 7: Timing measurement reference level is (VIH + VIL) / 2.
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VREF = +2.7V to +5.5V, GND = 0V, RL = 10k
, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
VDD = VREF = +3V and TA = +25°C.)
60
CONDITIONS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
From code 00 to code F0 hex
REF = 0.5Vp-p, VREF(DC) = 1.5V,
VDD = 3V, -3dB bandwidth
To 1/2LSB, from code 00 to code F0 hex
Code 00 to code FF hex
IDD < 5A
Code 80 hex to code 7F hex
To ±1/2LSB of final value of VOUT
ns
20
tWR
WR Pulse Width
ns
0
tDH
Data to WR Hold
ns
25
tDS
Data to WR Setup
ns
0
tAH
Address to WR Hold
ns
5
tAS
Address to WR Setup
A
0.001
1
Shutdown Current
A
190
360
IDD
Supply Current (Note 6)
V
2.7
5.5
VDD
Power-Supply Voltage
s
20
tSDN
Time to Shutdown
s
13
tSDR
Shutdown Recovery Time
V/s
0.6
Output Voltage Slew Rate
VRMS
60
Wideband Amplifier Noise
kHz
650
Multiplying Bandwidth
70
s
6
Output Settling Time (Note 3)
nVs
500
Channel-to-Channel Isolation
(Note 4)
nVs
0.5
Digital Feedthrough (Note 5)
nVs
90
Digital-to-Analog Glitch Impulse
REF = 2.5Vp-p at 1kHz, VREF(DC) = 1.5V,
VDD = 3V, code FF hex
Signal-to-Noise plus Distortion
Ratio
SINAD
dB
REF = 2.5Vp-p at 10kHz, VREF(DC) = 1.5V,
VDD = 3V, code FF hex
DYNAMIC PERFORMANCE
POWER SUPPLIES
DIGITAL TIMING (Figure 1) (Note 7)
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