參數(shù)資料
型號: MAX504ESD+T
廠商: Maxim Integrated Products
文件頁數(shù): 15/16頁
文件大?。?/td> 0K
描述: IC DAC 10BIT VOLT OUT 14-SOIC
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
設置時間: 25µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉換器數(shù)目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 14-SOIC
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): *
MAX504/MAX515
5V, Low-Power, Voltage-Output
Serial 10-Bit DACs
8
_______________________________________________________________________________________
10
FUNCTION
1
BIPOFF
Bipolar offset/gain
resistor
2
DIN
Serial data input
3
CLR
Clear. Asynchronously sets
DAC register to all 0s.
PIN
1
4
SCLK
Serial clock input
5
CS
Chip select, active low
6
DOUT
Serial data output for
daisy-chaining
7
DGND
Digital ground
2
3
8
AGND
Analog ground
9
REFIN
Reference input
4
5
6
REFOUT
Reference output,
2.048V. Connect to VDD
if not used.
11
VSS
Negative power supply
12
7
VOUT
DAC output
13
8
VDD
Positive power supply
14
RFB
Feedback resistor
MAX504
MAX515
NAME
____________________Pin Description
_______________Detailed Description
General DAC Discussion
The MAX504/MAX515 use an “inverted” R-2R ladder net-
work with a single-supply CMOS op amp to convert 10-bit
digital data to analog voltage levels (see
Functional
Diagram). The term “inverted” describes the ladder net-
work because the REFIN pin in current-output DACs is the
summing junction, or virtual ground, of an op amp.
However, such use would result in the output voltage
being the inverse of the reference voltage. The
MAX504/MAX515’s topology makes the output the same
polarity as the reference input.
An internal reset circuit forces the DAC register to reset
to all 0s on power-up. Additionally, a clear (CLR) pin,
when held low, sets the DAC register to all 0s. CLR
operates asynchronously and independently from the
chip select (CS) pin.
Buffer Amplifier
The output buffer is a unity-gain stable, rail-to-rail output,
BiCMOS op amp. Input offset voltage and CMRR are
trimmed to achieve better than 10-bit performance.
Settling time is 25s to 0.01% of final value. The output is
short-circuit protected and can drive a 2k
load with more
than 100pF load capacitance.
tCSH0
tCSS
tCH
tCL
tCSH1
tCSW
tDS
tDH
tDO
CS
SCLK
DIN
DOUT
tCS1
Figure 1. Timing Diagram
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