參數(shù)資料
型號(hào): MAX4820EUP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 外設(shè)及接口
英文描述: +3.3V/+5V, 8-Channel, Cascadable Relay Drivers with Serial/Parallel Interface
中文描述: 0.07 A BUF OR INV BASED PRPHL DRVR, PDSO20
封裝: 4.40 MM, MO-153ACT, TSSOP-20
文件頁(yè)數(shù): 7/13頁(yè)
文件大?。?/td> 351K
代理商: MAX4820EUP
Digital Interface
Serial Interface (MAX4820)
The serial interface consists of an 8-bit shift register
and parallel latch controlled by SCLK and
CS
. The
input to the shift register is an 8-bit word. Each data bit
controls one of the eight outputs, with the most signifi-
cant bit (D7) corresponding to OUT8 and the least sig-
nificant bit (D0) corresponding to OUT1 (see Table 1).
When
CS
is low (device is selected), data at DIN is
clocked into the shift register synchronously with
SCLK
s rising edge. Driving
CS
from low to high latches
the data in the shift register to the parallel latch.
DOUT is the output of the shift register. Data appears
on DOUT synchronously with SCLK
s falling edge and
is identical to the data at DIN delayed by eight clock
cycles. When shifting the input data, D7 is the first bit in
and out of the shift register.
While
CS
is low, the switches always remain in their pre-
vious state. Drive
CS
high after 8 bits of data have been
shifted in to update the output state and inhibit further
data from entering the shift register. When
CS
is high,
transitions at DIN and SCLK have no effect on the out-
put, and the first input bit (D7) is present at DOUT.
If the number of data bits entered while
CS
is low is
greater or less than 8, the shift register contains only
the last 8 data bits, regardless of when they were
entered.
The 3-wire serial interface is compatible with SPI, QSPI,
and MICROWIRE standards. The latch that drives the
analog switch is updated on the rising edge of
CS
,
regardless of SCLK
s state.
Parallel Interface (MAX4821)
The parallel interface consists of three address bits
(A0, A1, A2) and one level selector bit (LVL). The
address bits determine which output is updated, and
the level bit determines whether the addressed output
is switched on (LVL = high) or off (LVL = low). When
CS
is high, the address and level bits have no effect on the
state of the outputs. Driving
CS
from low to high latches
the address and level data to the parallel register and
updates the state of the outputs. Address data entered
after
CS
is pulled low is not reflected in the state of the
outputs following the next low-to-high transition on
CS
(Figure 2).
M
3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
_______________________________________________________________________________________
7
Table 1. Serial Input Address Map (MAX4820 Only)
DIN
OUT_
D0
D1
D2
D3
D4
D5
D6
D7
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
SCLK
DIN
DOUT
t
CSS
t
CL
t
CH
t
CSW
t
CSH
t
DO
t
ON
,
t
OFF
t
CSO
t
DS
t
DH
D7
D6
D1
D0
CS
OUT_
Figure 1. 3-Wire Serial-Interface Timing Diagram (MAX4820 only)
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MAX4820EUP+T 功能描述:功率驅(qū)動(dòng)器IC 3.3-5V 8Ch Cascade Relay Driver RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類(lèi)型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube
MAX4820EUP-T 功能描述:功率驅(qū)動(dòng)器IC RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類(lèi)型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube
MAX4821ETP 功能描述:功率驅(qū)動(dòng)器IC RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類(lèi)型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube
MAX4821ETP+ 功能描述:功率驅(qū)動(dòng)器IC 3.3-5V 8Ch Cascade Relay Driver RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類(lèi)型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube