參數(shù)資料
型號: MAX4736EGC+T
廠商: Maxim Integrated Products
文件頁數(shù): 8/10頁
文件大小: 0K
描述: IC SWITCH DUAL SPDT 12QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
功能: 開關(guān)
電路: 2 x SPDT
導(dǎo)通狀態(tài)電阻: 800 毫歐
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 1.6 V ~ 4.2 V
電流 - 電源: 1µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 12-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 12-QFN-EP(3x3)
包裝: 帶卷 (TR)
Detailed Description
The MAX4736 is a low 0.8Ω max (at V+ = 2.7V) onresis-
tance, low-voltage, dual SPDT analog switch that oper-
ates from a 1.6V to 4.2V single supply. CMOS switch
construction allows switching analog signals that range
from GND to V+.
When powered from a 2.7V supply, the 0.8Ω max RON
allows high continuous currents to be switched in a variety
of applications.
Applications Information
Proper power-supply sequencing is recommended for all
CMOS devices. Do not exceed the absolute maximum
ratings; stresses beyond the listed ratings can cause per-
manent damage to the devices. Always sequence V+ on
first, followed by NO_, NC_, or COM_.
Although it is not required, power-supply bypassing
improves noise margin and prevents switching noise
propagation from the V+ supply to other components. A
0.1μF capacitor, connected from V+ to GND, is adequate
for most applications.
Logic Inputs
The MAX4736 logic inputs can be driven up to 3.6V,
regardless of the supply voltage. For example, with a 1.8V
supply, IN_ can be driven low to GND and high to 3.6V.
Driving IN_ rail-to-rail minimizes power consumption.
Analog Signal Levels
Analog signals that range over the entire supply voltage
(V+ to GND) can be passed with very little change in
onresistance (see Typical Operating Characteristics). The
switches are bidirectional, so the NO_, NC_, and COM_
pins can be used as either inputs or outputs.
Layout
High-speed switches require proper layout and design
procedures for optimum performance. Reduce stray induc-
tance and capacitance by keeping traces short and wide.
Ensure that bypass capacitors are as close to the device
as possible. Use large ground planes where possible.
Figure 1. Switching Time
tr < 5ns
tf < 5ns
50%
0
VIN_ = VIH + 0.5V
tOFF
0
0.9 x V0UT
0.9 x VOUT
tON
VOUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
MAX4736
LOGIC
INPUT
RL
GND
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_ or NC_
IN_
NC_ or NO_
VOUT
V+
CL
VIN
COM_
MAX4736
0.6Ω, Low-Voltage, Single-Supply, Dual SPDT
Analog Switch
www.maximintegrated.com
Maxim Integrated │ 7
Test Circuits/Timing Diagrams
相關(guān)PDF資料
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