參數(shù)資料
型號(hào)： MAX4684EUB+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 4/10頁(yè)
文件大?。?/td> 0K
描述： IC SWITCH DUAL SPDT 10UMAX
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
功能： 開(kāi)關(guān)
電路： 2 x SPDT
導(dǎo)通狀態(tài)電阻： 800 毫歐
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 1.8 V ~ 5.5 V
電流 - 電源： 40µA
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-µMAX
包裝： 帶卷 (TR)
MAX4684/MAX4685
0.5
Ω
Ω/0.8Ω
Ω Low-Voltage, Dual SPDT
Analog Switches in UCSP
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS—+3V SUPPLY (continued)
(V+ = +2.7V to +3.3V, VIH = +1.4V, VIL = +0.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at +3V and +25°C.)
(Notes 3, 9, 10)
PARAMETER
SYMBOL
CONDITIONS
TA
MIN
TYP
MAX
UNITS
+25
°C
25
30
Turn-Off Time
tOFF
V+ = 2.7V, VNO_ or VNC_ = 1.5V;
RL = 50
Ω; CL = 35pF; Figure 2
E40
ns
Break-Before-Make
Delay
tBBM
V+ = 2.7V, VNO_, or VNC_ = 1.5V;
RL = 50
Ω; CL = 35pF; Figure 3
E
2
15
ns
Charge Injection
Q
COM_ = 0; RS = 0; CL = 1nF; Figure 4
+25
°C
200
pC
Off-Isolation (Note 8)
VISO
CL = 5pF; RL = 50
Ω; f = 100kHz;
VCOM_ = 1VRMS; Figure 5
+25
°C
-64
dB
Crosstalk
VCT
CL = 5pF; RL = 50
Ω; f = 100kHz;
VCOM_ = 1VRMS; Figure 5
+25
°C
-68
dB
Total Harmonic
Distortion
THD
RL = 600
Ω, IN_ = 2Vp-p, f = 20Hz to
20kHz
+25
°C0.03
%
NC_ Off-Capacitance
CNC_(OFF)
f = 1MHz; Figure 6
+25
°C
84
pF
NO_ Off-Capacitance
CNO_(OFF)
f = 1MHz; Figure 6
+25
°C
37
pF
NC_ On-Capacitance
CNC_(ON)
f = 1MHz; Figure 6
+25
°C
190
pF
NO_ On-Capacitance
CNO_(ON)
f = 1MHz; Figure 6
+25
°C
150
pF
DIGITAL I/O
Input Logic High
VIH
E1.4
V
Input Logic Low
VIL
E
0.5
V
IN_ Input Leakage
Current
IIN_VIN_ = 0 or V+
E
-1
1
A
POWER SUPPLY
Power-Supply Range
V+
E
1.8
5.5
V
+25
°C
-50
0.04
50
Supply Current (Note 4)
I+
V+ = 5.5V; VIN_ = 0 or V+
E
-200
200
nA
Note 3:
The algebraic convention used in this data sheet is where the most negative value is a minimum and the most positive
value a maximum.
Note 4:
Guaranteed by design.
Note 5:
ΔRON = RON(MAX) - RON(MIN), between NC1 and NC2 or between NO1 and NO2.
Note 6:
Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal ranges.
Note 7:
Leakage parameters are 100% tested at TA = +85°C, and guaranteed by correlation over rated temperature range.
Note 8:
Off-isolation = 20log10 (VCOM / VNO), VCOM = output, VNO = input to off switch.
Note 9:
UCSP and TDFN parts are 100% tested at +25°C only and guaranteed by design and correlation at the full hot-rated
temperature.
Note 10: -40°C specifications are guaranteed by design.
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