參數(shù)資料
型號: MAX4613EEE+
廠商: Maxim Integrated Products
文件頁數(shù): 7/10頁
文件大?。?/td> 0K
描述: IC SWITCH QUAD SPST 16QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 100
功能: 開關(guān)
電路: 4 x SPST - NC/NO
導(dǎo)通狀態(tài)電阻: 70 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 4.5 V ~ 40 V,±4.5 V ~ 20 V
電流 - 電源: 1µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 管件
MAX4613
Applications Information
General Operation
1) Switches are open when power is off.
2) IN_, D_, and S_ should not exceed V+ or V-, even
with the power off.
3) Switch leakage is from each analog switch terminal
to V+ or V-, not to other switch terminals.
Operation with Supply Voltages
Other than ±15V
Using supply voltages less than ±15V will reduce the
analog signal range. The MAX4613 operates with
±4.5V to ±20V bipolar supplies or with a +4.5V to +40V
single supply; connect V- to GND when operating with
a single supply. Also, all device types can operate with
unbalanced supplies such as +24V and -5V. VL must
be connected to +5V to be TTL compatible, or to V+ for
CMOS-logic level inputs. The Typical Operating
Characteristics graphs show typical on-resistance with
±20V, ±15V, ±10V, and ±5V supplies. (Switching times
increase by a factor of two or more for operation at ±5V.)
Overvoltage Protection
Proper power-supply sequencing is recommended
for all CMOS devices. Do not exceed the absolute
maximum ratings because stresses beyond the list-
ed ratings may cause permanent damage to the
devices. Always sequence V+ on first, followed by
VL, V-, and logic inputs. If power-supply sequencing
is not possible, add two small, external signal
diodes in series with supply pins for overvoltage
protection (Figure 1). Adding diodes reduces the
analog signal range to 1V below V+ and 1V above
V-, but low switch resistance and low leakage char-
acteristics are unaffected. Device operation is
unchanged, and the difference between V+ and V-
should not exceed +44V.
Quad, SPST Analog Switch
6
_______________________________________________________________________________________
Pin Description
PIN
DIP/SO/TSSOP
THIN QFN
NAME
FUNCTION
1, 8, 9, 16
6, 7, 14, 15
IN1–IN4
Logic Control Input
2, 7, 10, 15
5, 8, 13, 16
D1–D4
Analog-Switch Drain Output
3, 6, 11, 14
1, 4, 9, 12
S1–S4
Analog-Switch Source Output
4
2
V-
Negative-Supply Voltage Input
5
3
GND
Ground
12
10
VL
Logic-Supply Voltage Input
13
11
V+
Positive-Supply Voltage Input—Connected to Substrate
EP
PAD
Exposed Pad. Connect PAD to V+.
Figure 1. Overvoltage Protection Using External Blocking Diodes
V+
D
V-
S
Vg
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