參數(shù)資料
型號: MAX4524LEUB+T
廠商: Maxim Integrated Products
文件頁數(shù): 9/12頁
文件大小: 0K
描述: IC MUX/SW ANLG CMOS LV 10UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準包裝: 2,500
功能: 多路復(fù)用器/多路分解器
電路: 1 x 4:1
導(dǎo)通狀態(tài)電阻: 80 歐姆
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 2 V ~ 12 V
電流 - 電源: 1µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 帶卷 (TR)
MAX4524L/MAX4525L
Detailed Description
The MAX4524L/MAX4525L are low-voltage, single-sup-
ply CMOS analog switches that operate from a single
supply of +2V to +12V. Operation with a +12V supply
optimizes the performance by reducing their on-resis-
tance to 100
. The MAX4524L is configured as a 4-
channel multiplexer/demultiplexer and the MAX4525L is
a double-pole/double-throw (DPDT) switch. These
devices have an inhibit input (INH) to simultaneously
open all signal paths. Each switch can handle rail-to-
rail analog signals. The off-leakage current is typically
only 0.1nA at +25°C and 10nA (max) over temperature.
All digital inputs have 0.8V to 2.0V logic-level thresh-
olds, ensuring TTL/CMOS-logic compatibility when
using a single +12V supply.
Applications Information
Power-Supply Considerations
The MAX4524L/MAX4525Ls’ construction is typical of
most CMOS analog switches. The supply input, V+, is
used to power the internal CMOS switches and set the
limits of the analog voltage on any switch. Reverse ESD
protection diodes are internally connected between
each analog signal pin and both V+ and GND. If any
analog signal exceeds V+ or goes below GND, one of
these diodes conducts. During normal operation, these
reverse-biased ESD diodes leak, forming the only cur-
rent drawn from V+ or GND. Virtually all the analog
leakage current comes from the ESD diodes. Although
the ESD diodes on a given signal pin are identical, and
therefore fairly well balanced, they are reverse biased
differently. Each is biased by either V+ or GND and the
analog signal. This means that leakage varies as the
signal varies. The difference in the two diode leakages
to the V+ and GND pins constitutes the analog signal-
path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not
to the other switch terminal. This is why both sides of a
given switch can show leakage currents of either the
same or opposite polarity.
There is no connection between the analog signal
paths and GND. V+ and GND power the internal logic
and logic-level translators, and set both the input and
output logic limits. The logic-level translators convert
the logic levels into switched V+ and GND signals to
drive the gates of the analog signals. This drive signal
is the only connection between the logic supplies (and
signals) and the analog supplies.
Low-Voltage, Single-Supply Analog
Multiplexers/Switches
6
_______________________________________________________________________________________
Test Circuits/Timing Diagrams
50%
tOFF
V+
0V
VNO0
VOUT
VINH
0V
90%
tON
50%
tOFF
V+
0V
VNO_
VOUT
VINH
0V
90%
tON
VINH
V+
VOUT
GND
V+
ADDB
ADDA
INH
NO0
NO1–NO3
COM
V+
MAX4524L
300
50
35pF
V+
VOUT
GND
V+
ADD
INH
NO_
NC_
COM_
V+
MAX4525L
300
35pF
50
Figure 1. Inhibit Switching Times
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