參數(shù)資料
型號: MAX4456EPL
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 運動控制電子
英文描述: Low-Cost 4x4, 8x4, 8x8 Video Crosspoint Switches
中文描述: 8-CHANNEL, CROSS POINT SWITCH, PDIP40
封裝: 0.600 INCH, PLASTIC, MS-011AC, DIP-40
文件頁數(shù): 8/16頁
文件大小: 249K
代理商: MAX4456EPL
M
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
8
_______________________________________________________________________________________
32-Bit Serial-Interface Mode (MAX4456)
In serial mode (SER/
PAR
= V
CC
), all first-rank registers
are loaded with data, making it unnecessary to specify
an output address (A2, A1, A0). The input data format
is D3–D0, starting with OUT0 and ending with OUT7 for
32 total bits. Only codes 0000 through 1010 are valid.
Code 1010 disables a buffer, while code 1001 enables
it. After data is shifted into the 32-bit first-rank register, it
is transferred to the second rank by LATCH (Table 2),
which updates the switches.
SERIAL /
PARALLEL
D3
H
X
L
H
L
(A2), A1,
A0
X
Output
Buffer
Address
Output
Buffer
Address
D1
Serial
Output
Parallel
Input
Parallel
Input
D2
X
Parallel
Input
Parallel
Input
D0
Serial Input
Parallel
Input
Parallel
Input
COMMENT
Serial Mode
Parallel Mode,
D0–D2 = Control Code
Parallel Mode,
D0–D2 = Input Address
L
Table 3. Input/Output Line Configurations
X = Don’t care, H = 5V, L = 0V
( ) are for MAX4456 only.
Table 2. Serial-Interface Mode Functions
D3–D0
FUNCTION
0000 to 0111
Connect the selected buffer to the input
channel selected by D3–D0. Note that 0100
through 0111 are not valid for the MAX4359.
1000
Connect the input of the selected buffer to
GND. Note: If the buffer output remains
on, its input is its offset voltage.
1001
Turn on the selected buffer and connect
its input to GND. Use this code to turn on
buffers after power is applied. The default
power-up state is all buffers disabled.
1010
Shut off the selected buffer at the speci-
fied channel, and erase data stored in the
2nd rank of registers. The 2nd rank now
holds the command word 1010.
1011 to 1111
Do not use these codes in the serial-inter-
face mode. They inhibit the latching of the
2nd-rank registers, which prevents proper
data loading.
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