參數(shù)資料
型號: MAX4245AUT+T
廠商: Maxim Integrated Products
文件頁數(shù): 11/17頁
文件大小: 0K
描述: IC OPAMP GP R-R 1MHZ LP SOT23-6
其它有關(guān)文件: Automotive Product Guide
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
放大器類型: 通用
電路數(shù): 1
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 0.4 V/µs
增益帶寬積: 1MHz
電流 - 輸入偏壓: 10nA
電壓 - 輸入偏移: 400µV
電流 - 電源: 375µA
電流 - 輸出 / 通道: 30mA
電壓 - 電源,單路/雙路(±): 2.5 V ~ 5.5 V,±1.25 V ~ 2.75 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-6
供應(yīng)商設(shè)備封裝: SOT-6
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX4245AUT+TDKR
MAX4245/MAX4246/MAX4247
Ultra-Small, Rail-to-Rail I/O with Disable,
Single-/Dual-Supply, Low-Power Op Amps
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V, VSS = 0V, VCM = 0V, VOUT = VDD / 2, RL connected from OUT to VDD / 2, SHDN_ = VDD (MAX4245/MAX4247 only),
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Gain-Bandwidth Product
GBW
1.0
MHz
Phase Margin
φM
70
degrees
Gain Margin
GM
20
dB
Slew Rate
SR
0.4
V/s
Input Voltage-Noise Density
en
f = 10kHz
52
nV/√Hz
Input Current-Noise Density
in
f = 10kHz
0.1
pA/√Hz
Capacitive-Load Stability
CLOAD
AV = 1 (Note 3)
470
pF
Shutdown Delay Time
t(SH)
(Note 2)
3
s
Enable Delay Time
t(EN)
(Note 2)
4
s
Power-On Time
tON
4s
Input Capacitance
CIN
2.5
pF
Total Harmonic Distortion
THD
f = 10kHz, VOUT = 2Vp-p, AV = +1,
VDD = +5.0V, Load = 100k to VDD/2
0.01
%
Settling Time to 0.01%
tS
VOUT = 4V step, VDD = +5.0V, AV = +1
10
s
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V, VSS = 0V, VCM = 0V, VOUT = VDD / 2, RL connected from OUT to VDD / 2, SHDN_ = VDD (MAX4245/MAX4247 only),
TA = -40°C to +125°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage Range
VDD
Inferred from PSRR test
2.5
5.5
V
Supply Current (Per Amplifier)
IDD
VDD = +2.7V
800
A
Supply Current in Shutdown
ISHDN_
SHDN_ = VSS (Note 2)
1
A
Input Offset Voltage
VOS
VSS ≤ VCM ≤ VDD (Note 4)
±3.0
mV
Input Offset Voltage Drift
TCVOS
VSS ≤ VCM ≤ VDD (Note 4)
±2
V/°C
Input Bias Current
IB
VSS ≤ VCM ≤ VDD (Note 4)
±100
nA
Input Offset Current
IOS
VSS ≤ VCM ≤ VDD (Note 4)
±10
nA
Input Common-Mode Voltage
Range
VCM
Inferred from CMRR test (Note 4)
VSS
VDD
V
Common-Mode Rejection Ratio
CMRR
VSS ≤ VCM ≤ VDD (Note 4)
60
dB
Power-Supply Rejection Ratio
PSRR
2.5V ≤ VDD ≤ 5.5V
70
dB
Large-Signal Voltage Gain
AV
VSS + 0.2V ≤ VOUT ≤ VDD - 0.2V,
RL = 2k
85
dB
Output Voltage Swing High
VOH
Specified as VDD - VOUT, RL = 2k
90
mV
Output Voltage Swing Low
VOL
Specified as VOUT - VSS, RL = 2k
90
mV
Output Leakage Current in
Shutdown
IOUT(SH)
Device in Shutdown Mode (SHDN_ = VSS),
VSS ≤ VOUT ≤ VDD (Note 3)
±1.0
A
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