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參數(shù)資料
| 型號： | MAX3992UTG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DATA RECOVERY W/EQ 24-TQFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | SONET/SDH.XFP 光學(xué)接收器 |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 693.5MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-TQFN-EP（4x4） |
| 包裝： | 帶卷 (TR) |
Loss-of-Lock Monitor
The LOL output indicates that the frequency difference
between the recovered clock and the reference clock is
excessive. LOL may assert due to excessive jitter at the
data input, incorrect frequency, or loss of input data.
The LOL detector monitors the frequency difference
between the recovered clock and the reference clock.
The LOL output is asserted high when the frequency
difference exceeds 650ppm.
Loss-of-Signal Monitor
The LOS output indicates a loss of input data. Set VTH
>500mV. When the input signal is removed (<50mV),
LOS will be asserted high.
Reference Clock Input
The REFCLK inputs are internally terminated and self-
biased to allow AC-coupling. The input impedance is
100 single-ended (200 differential). The REFCLK
inputs of the MAX3991 and MAX3992 should be con-
nected close together in parallel. The impedance look-
ing into the parallel combination is 100 differential.
This allows both the MAX3991 and MAX3992 to easily
interface with one reference clock without using addi-
tional components. See Figure 4.
Design Procedure
Modes of Operation
The MAX3992 has a standby mode and jitter test mode
in addition to its normal operating mode. Standby is
used to conserve power. In the standby mode, the
power consumption of the MAX3992 falls below 40% of
the normal-operation power consumption. The jitter test
mode enables the SCLK outputs to clock a BERT when
testing jitter generation, jitter transfer, and jitter toler-
ance. The FCTL1 and FCTL2 TTL inputs are used to
select the mode of operation as shown in Table 3.
Serial Data Rate and
Reference Clock Frequency
Input Configuration
The SDI± inputs of the MAX3992 are current-mode
logic (CML) compatible. The inputs have internal 50
terminations for minimum external components. See
Figure 5 for the input structure. For additional informa-
tion on logic interfacing, refer to Maxim Application
Note HFAN 1.0: Introduction to LVDS, PECL, and CML.
Output Configuration
The MAX3992 uses CML for its high-speed digital out-
puts (SDO± and SCLKO±). The configuration of the out-
put circuit includes internal 50 back terminations to
VCC. See Figure 6 for the output structure. CML outputs
may be terminated by 50 to VCC, or by 100 differen-
tial impedance. The relation of the output polarity to input
can be reversed using the POL pin. For additional infor-
mation on logic interfacing, refer to Maxim Application
Note HFAN 1.0: Introduction to LVDS, PECL, and CML.
MAX3992
10Gbps Clock and Data Recovery
with Equalizer
_______________________________________________________________________________________
9
MAX3991
MAX3992
200
50W
REFERENCE
CLOCK
50W
REFERENCE
CLOCK
TRANSCEIVER TERMINATION
TRANSMITTER-ONLY TERMINATION
200
Figure 4. Reference Clock Termination
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