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參數(shù)資料
| 型號： | MAX395 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 1:10 LVDS Serdes Receiver 100 - 660Mbps 28-SSOP -40 to 85 |
| 中文描述： | 串行控制、低電壓、8通道、SPST開關(guān) |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 123K |
| 代理商： | MAX395 |
M
S erially Controlled, Low-Voltage,
8-Channel S PS T S witc h
8
_______________________________________________________________________________________
Note 1:
The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 2:
R
ON
= R
ON(max)
- R
ON(min)
. On-resistance match between channels and on-resistance flatness are guaranteed only with
specified voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as
measured over the specified analog signal range.
Note 3:
Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp.
Note 4:
Guaranteed by design.
Note 5:
Leakage testing at single supply is guaranteed by testing with dual supplies.
Note 6:
See Figure 6. Off isolation = 20log
10
V
COM
/V
NO
, V
COM
= output. NO = input to off switch.
Note 7:
Between any two switches. See Figure 3.
TIMING CHARACTERISTICS—Single +3V Supply (Figure 1)
(V+ = +3.0V to +3.6V, V- = 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
SERIAL DIGITAL INTERFACE
SCLK Frequency
RESET Minimum Pulse Width
t
RW
105
ns
T
A
= +25°C
Allowable Fall Time at DIN,
SCLK (Note 4)
t
SCF
2
μs
20% of V+ to 70% of V+,
C
L
= 10pF
C, E, M
Fall Time of DOUT (Note 4)
t
DF
300
ns
20% of V+ to 70% of V+,
C
L
= 10pF
C, E, M
Rise Time of DOUT (Note 4)
t
DR
300
ns
20% of V+ to 70% of V+,
C
L
= 10pF
20% of V+ to 70% of V+,
C
L
= 10pF
C, E, M
Allowable Rise Time at DIN,
SCLK (Note 4)
t
SCR
2
μs
C, E, M
DIN Data Valid after Falling SCLK
(Note 4)
t
DO
400
ns
Data Hold Time (Note 4)
Data Setup Time (Note 4)
t
DS
t
DH
200
0
38
-38
150
ns
ns
50% of SCLK to 10% of
DOUT, C
L
= 10pF
SCLK Low Time (Note 4)
t
CL
C, E, M
190
ns
T
A
= +25°C
C, E, M
C, E, M
PARAMETER
SYMBOL
MIN
TYP
MAX
(Note 2)
UNITS
C, E, M
SCLK High Time (Note 4)
CS Lag Time (Note 4)
t
CSH2
t
CH
240
190
ns
ns
CS Lead Time (Note 4)
Cycle Time (Note 4)
f
SCLK
t
CH
+ t
CL
t
CSS
0
2.1
MHz
ns
480
240
ns
C, E, M
C, E, M
C, E, M
C, E, M
C, E, M
CONDITIONS
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