參數(shù)資料
型號: MAX3877
廠商: Maxim Integrated Products, Inc.
英文描述: Half-Duplex LVDM Transceiver 8-SOIC -40 to 85
中文描述: 2.5Gbps、+3.3V時鐘與數(shù)據(jù)再定時IC,帶有垂直調(diào)節(jié)閾值
文件頁數(shù): 4/16頁
文件大?。?/td> 550K
代理商: MAX3877
M
2.5Gbps, +3.3V Clock and Data Retiming ICs
with Vertical Threshold Adjust
4
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40
°
C to +85
°
C, unless otherwise noted. Typical values are at V
CC
= +3.3V and T
A
= +25
°
C.)
(Note 6)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f = 70kHz
3.18
f = 100kHz (see
Jitter Tolerance
graph in
Typical Operating Characteristics
)
2.75
f = 1MHz
0.41
0.67
Jitter Tolerance
f = 10MHz
0.36
0.45
UIp-p
0.003
0.006
UI
RMS
Jitter Generation
J
GEN
Jitter bandwidth = 12kHz to 20MHz
0.026
0.056
UIp-p
Clock Output Edge Speed
(20% to 80%)
120
ps
Data Output Edge Speed
(20% to 80%)
120
ps
Tolerated Consecutive Identical
Digits
BER
10
-10
2000
bits
100kHz to 2.5GHz
17
Input Return Loss (SDI
±
, SLBI
±
)
2.5GHz to 4.0GHz
14.5
dB
PLL Acquisition Time
14
ms
LOS Assert Time
1.65
μs
LOS Deassert Time
4.0
μs
Low-Frequency Cutoff for
DC-Cancellation Loop
C
PWD
= 0.1μF
10
kHz
HOLDOVER SPECIFICATION
VCO Frequency Drift Rate in the
Absence of Data
df/dt
C
FIL
= 1μF
6.2
kHz/μs
PHASE ADJUST SPECIFICATION
Minimum Phase Adjust Range
(Note 7)
-60
+60
ps
Phase Adjust Stability
(Note 8)
-8
+8
ps
Note 1:
At T
A
= -40
°
C, DC characteristics are guaranteed by design and characterization.
Note 2:
Excluding PECL output termination, CML outputs open.
Note 3:
Jitter specifications are guaranteed for this data input voltage range, measured by connecting THADJ to V
CC
. Guaranteed
by design and characterization.
Note 4:
Jitter specifications are guaranteed when input threshold is set to
30% of the differential input swing. Measured with edge
speed
150ps (Figure 3). Guaranteed by design and characterization.
Note 5:
Threshold setting stability is guaranteed by design and characterization.
Note 6:
AC characteristics are guaranteed by design and characterization.
Note 7:
Phase adjust is disabled when PHADJ is connected to V
CC
.
Note 8:
Phase adjust stability is guaranteed over temperature and power-supply variation.
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