參數(shù)資料
型號(hào): MAX3768CUB+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/17頁
文件大?。?/td> 0K
描述: IC AMP LIMITING 1.25GBPS 10-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 限幅放大器
應(yīng)用: 光纖學(xué)網(wǎng)絡(luò)
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 帶卷 (TR)
MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
+3.0V to +5.5V, 1.25Gbps/2.5Gbps
Limiting Amplifiers
12
______________________________________________________________________________________
The buffer’s output impedance is determined by the par-
allel combination of internal and external pullup resistors,
which are chosen to match the impedance of the trans-
mission line (Figure 1). The output buffer can be AC- or
DC-coupled to the load.
PECL Output Buffer
The MAX3268/MAX3269/MAX3768 offer an industry-
standard PECL output. The PECL outputs should be
terminated to VCC - 2V. Figure 6 shows the PECL out-
put circuit. The squelch function forces OUT+ to a high
level and OUT- to a low level when the input is below
the programmed LOS threshold. In the 10-pin MAX,
SQUELCH is left unconnected.
__________________Design Procedure
Program the LOS Assert Threshold
The loss-of-signal threshold is programmed by external
resistor RTH. See the LOS Threshold vs. RTH graph in
the Typical Operating Characteristics.
Select the Coupling Capacitors
The coupling capacitors (CIN, COUT) should be select-
ed to minimize the receiver’s deterministic jitter. Jitter is
minimized when the input low-frequency cutoff (fIN) is
placed at a low frequency:
fIN = 1 / [2π(50)(C)]
For Fibre Channel, Gigabit Ethernet, or other applica-
tions using 8B/10B data coding, select (CIN, COUT) ≥
0.01F, which provides fIN < 320kHz. For ATM/SONET
or other applications using scrambled NRZ data, select
(CIN,COUT) ≥ 0.1F, which provides fIN < 32kHz.
Select the Offset-Correction Capacitor
(MAX3264/MAX3265 TSSOP Only)
To maintain stability, it is important to keep a one-
decade separation between fIN and the low-frequency
cutoff (fOC) associated with the DC-offset-correction cir-
cuit.
fOC = 75 / [2π 60k (CAZ + 100pF)]
= 200 x 10 -6 / (CAZ + 100pF)
For Fibre Channel, Gigabit Ethernet, or other applica-
tions using 8B/10B data coding, leave pins CAZ1, and
CAZ2 open (fOC = 2MHz). For ATM/SONET or other
applications using scrambled NRZ data, select CAZ
0.1F, which typically provides fOC = 2kHz.
GND
ESD
STRUCTURES
VCC
OUT-
OUT+
Figure 6. PECL Output Circuit
GND
LEVEL
ESD
STRUCTURES
VCC
100
OUT-
OUT+
Figure 7. CML Output Circuit
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