參數(shù)資料
型號： MAX3676EHJ+T
廠商： Maxim Integrated Products
文件頁數(shù)： 9/15頁
文件大?。?/td> 0K
描述： IC CLOCK RECOVERY 32-TQFP
產品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
類型： 時鐘和數(shù)據(jù)恢復（CDR），多路復用器
PLL： 是
主要目的： SONET/SDH
輸入： PECL
輸出： PECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-TQFP
供應商設備封裝： 32-TQFP（5x5）
包裝： 帶卷 (TR)
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
_______________________________________________________________________________________
3
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.)
(Notes 2, 3)
Note 2: AC parameters are guaranteed by design and characterization.
Note 3: The MAX3676 is characterized with a PRBS of 223 - 1 maintaining a BER of
≤ 10-10 having a confidence level of 99.9%.
Note 4: A lower minimum input voltage of 2mVP-P is achievable; however, the LOP hysteresis is not guaranteed below 3.6mVP-P.
Note 5: Hysteresis = 20log(VRELEASE/VASSERT).
Note 6: R1 = 20k
Ω, R2 = 3.0kΩ, resulting in VRELEASE ≈ 3.6mVP-P.
Note 7: Small-signal bandwidth cannot be measured directly.
Note 8: RSSI slope = [VRSSI2 - VRSSI1]/[20log (VID2/VID1)].
Note 9: 1UI = 1 unit interval = (622.08MHz)-1 = 1.608ns.
Note 10: At jitter frequencies <10kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications. The low-frequency
jitter tolerance outperforms the instrument’s measurement capability.
Note 11: See
Typical Operating Characteristics for worst-case distribution.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
RSSI Output Voltage
1.40
Limiting Amplifier Small-
Signal Bandwidth
BW
650
MHz
Power-Detect Hysteresis
36
dB
Input-Referred Noise
VN
80
μVRMS
Threshold Voltage
VTH
1.41
V
Differential Input Voltage
Range
VID
0.003
1.2000
VP-P
CONDITIONS
(ADI+) - (ADI-) = 2mVP-P
(Note 7)
(Notes 5, 6)
ADI inputs
(Note 6)
BER < 10-10, ADI inputs (Note 4)
1.93
V
(ADI+) - (ADI-) = 20mVP-P
Jitter-Transfer Peaking
0.03
0.08
dB
Maximum Consecutive Input
Run Length (1 or 0)
1200
Bits
CF = 2.2μF
8.9
CF = 2.2μF
(Note 11)
3.64
Jitter Tolerance (Note 10)
0.55
0.77
0.45
0.69
CF = 2.2μF
Loop Bandwidth
250
500
kHz
26
RSSI Linearity
±0.7
%
(ADI+) - (ADI-) = 2mVP-P to 50mVP-P
RSSI Slope
mV/dB
(ADI+) - (ADI-) = 2mVP-P to 50mVP-P
(Note 8)
UI
f = 10kHz
f = 25kHz
f = 250kHz
f = 1MHz
CF = 2.2μF
Jitter Generation (Note 9)
2.0
2.6
mUI
LOP Threshold Accuracy
-2
+2
dB
(Note 6)
Clock Transition Time
tr, tf
205
245
ps
20% to 80%
Data Transition Time
tr, tf
180
230
ps
20% to 80%
Serial Clock-to-Q Delay
tCLK-Q
140
275
400
ps
Serial Clock Frequency
fSCLK
622.08
MHz
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